Deep Submicron CMOS Scaling 1990s Scale the Gate Oxide Toward Its Tunneling Limit

# Deep Submicron CMOS Scaling (1990s): Step 5 — Scale the Gate Oxide Toward Its Tunneling Limit

## 1. Why the Oxide Has to Thin Along With Everything Else

Gate oxide capacitance per unit area sets how strongly the gate voltage controls channel charge, and that control has to improve roughly in step with shrinking channel length to maintain adequate transconductance and to suppress the short-channel threshold-rolloff effects the `mosfet_scaling_1970s` series' later steps already flagged as a scaling-limiting concern. The direct way to raise gate capacitance without changing the dielectric material is to make the oxide thinner, and 1990s deep submicron nodes pushed gate oxide thickness down from several tens of nanometers in earlier generations toward the single-digit-nanometer range by the decade's end.

## 2. Where Thinning Starts to Fight Back

Silicon dioxide's insulating behavior depends on the gate oxide being thick enough that an electron attempting to cross it by quantum tunneling has a vanishingly small probability of success. As oxide thickness falls into roughly the 3-to-5 nanometer range and below, that probability stops being negligible: a measurable direct-tunneling leakage current begins to flow from gate to channel even with no intentional conduction path, growing exponentially as thickness drops further. This is a fundamentally different failure mode from the hot-carrier wearout Steps 2 through 4 addressed — tunneling leakage is present from time zero in every device at a given thickness, not something that accumulates over the device's life, and it cannot be reduced by doping-profile grading at all, only by keeping the oxide thicker or changing the dielectric material.

## 3. The 1990s Trade Between Performance and Leakage

Thinner oxide gives more gate control, higher transconductance, and better suppression of short-channel threshold effects — all genuine performance wins. But each increment of thinning below the tunneling threshold also increases static gate leakage, which adds to a chip's total power consumption even when its transistors are not switching, and in sufficiently leaky cases can create local heating or contribute to long-term oxide wearout through a related but distinct degradation path from hot-carrier injection. 1990s process generations settled on oxide thicknesses that balanced these effects for the voltage and performance targets of their era, accepting a small but non-zero tunneling leakage budget rather than either over-thickening the oxide (losing performance) or under-thickening it (losing power efficiency and long-term reliability) — a balance this series' voltage-scaling steps (17 and 18) revisit from the supply-voltage side of the same trade.

## 4. A Limit the 1990s Approached but Did Not Yet Hit

By the end of the deep submicron 1990s window this series covers, gate oxides were thin enough that tunneling leakage was a recognized, budgeted contributor to chip power, but not yet the dominant leakage mechanism it would become in the following decade, when high-k dielectric replacements became necessary — a development this series intentionally leaves for a future scaling-era series rather than anticipating it here.

Tunneling Leakage Rises Exponentially Below a Few Nanometers gate leakage current density against gate oxide thickness, log scale measured static gate leakage (exponential rise below threshold) gate capacitance per unit area (rises smoothly as thickness falls) the point where thinning further costs more leakage than it buys capacitance oxide thickness decreases left to right tunneling leakage is present from time zero — not a wearout mechanism process generations choose a thickness that budgets, not eliminates, this leakage
Two Different Oxide Failure Modes, Not One distinguishing time-zero tunneling leakage from time-dependent hot-carrier wearout THICKER OXIDE more gate control margin, lower leakage, weaker short-channel suppression TUNNELING LEAKAGE present immediately at any sufficiently thin thickness, grows exponentially HOT-CARRIER WEAROUT accumulates over operating life, addressed separately by LDD grading thinning the oxide trades short-channel control for static power — a different axis from Steps 2-4

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