Deep Submicron CMOS Scaling 1990s Scale Multilevel Interconnect and Adopt Tungsten Plugs

# Deep Submicron CMOS Scaling (1990s): Step 9 — Scale Multilevel Interconnect and Adopt Tungsten Plugs

## 1. More Metal Layers, a Harder Via Problem

As logic density grew through deep submicron scaling, the number of metal interconnect layers needed to route a chip's signals grew with it — a 1990s high-end logic process might use three to five metal layers where an 1980s process used one or two. Connecting one metal layer to the next, or metal to the silicided diffusion or gate contact below it, requires filling a vertical via or contact hole with conductor, and as hole diameters shrank toward and below one micron, these holes developed aspect ratios (depth to width) that aluminum — the standard interconnect metal through most of this era — could not reliably fill using the sputtering deposition techniques that worked fine for the wider, shallower contacts of earlier generations.

## 2. Why Aluminum Struggles in a Narrow, Deep Hole

Sputtered aluminum deposits preferentially on upper surfaces and the tops of via sidewalls before it reaches the bottom of a narrow, deep hole, a geometric shadowing effect that gets worse as aspect ratio increases. The result in high-aspect-ratio deep submicron vias is voiding — incompletely filled holes with internal gaps — which raises contact resistance unpredictably and can cause early electrical failure, exactly the kind of reliability risk a process qualifying hot-carrier and oxide lifetimes elsewhere (Steps 2 through 6) could not also tolerate at the contact level.

## 3. The Tungsten Plug Solution

The fix was to stop trying to fill the narrowest, deepest holes — the contact to the silicon/silicide below and often the first via level above it — with aluminum at all, and instead fill them with chemical-vapor-deposited (CVD) tungsten, a process that fills from the bottom up conformally rather than shadowing from the top, giving void-free fill even in high-aspect-ratio holes. A thin titanium/titanium-nitride liner is typically deposited first to promote adhesion and act as a diffusion barrier, then tungsten is deposited to overfill the hole, and the excess tungsten on the flat surface outside the holes is removed — originally by a blanket etch-back, and increasingly through the 1990s by the chemical-mechanical polishing process Step 12 of this series covers in detail.

## 4. A Hybrid Interconnect Stack, Not a Full Material Change

Through most of the 1990s window this series covers, the resulting interconnect stack is a hybrid: tungsten plugs handle the narrowest, deepest contacts and lower vias where aluminum cannot reliably fill, while aluminum (or an aluminum-copper alloy for electromigration resistance) continues to carry the wider, shallower horizontal metal runs on each layer. This hybrid approach bought the 1990s industry several more generations of reliable multilevel interconnect without requiring a full switch to an entirely new interconnect metal — a switch whose motivating pressures Step 11 of this series covers, even though full copper adoption itself lies just past this series' window.

Via Fill Quality Diverges as Aspect Ratio Rises contact/via void fraction against hole aspect ratio, aluminum vs. CVD tungsten sputtered aluminum — voiding rises sharply with aspect ratio CVD tungsten — void-free fill holds flat across aspect ratios the aspect ratio past which aluminum alone becomes unreliable via aspect ratio (depth / width) increases left to right tungsten's bottom-up conformal fill avoids aluminum's top-shadowing void risk narrowest, deepest contacts switch to tungsten; wider runs stay aluminum
A Hybrid Interconnect Stack where tungsten plugs and aluminum lines each do their job in a 1990s multilevel stack SILICIDED CONTACT narrowest, deepest hole — tungsten plug with Ti/TiN liner LOWER VIA LEVELS high aspect ratio — tungsten plug fills without voiding HORIZONTAL METAL RUNS wider, shallower — aluminum (or Al-Cu alloy) continues to carry signal a hybrid stack, not a wholesale material replacement, through most of the 1990s

Take deep submicron cmos scaling 1990s scale multilevel interconnect and adopt tungsten plugs further

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