Deep Submicron CMOS Scaling 1990s Adopt Chemical Mechanical Polishing for Planarization

# Deep Submicron CMOS Scaling (1990s): Step 12 — Adopt Chemical-Mechanical Polishing for Multilevel Planarization

## 1. Why Flat Matters More as Layers Stack Up

A single metal or dielectric layer deposited over an already-patterned surface inherits that surface's topography — bumps over existing features, dips over gaps between them. For a process with only one or two metal layers, this topography is manageable; subsequent lithography can tolerate some underlying unevenness. As deep submicron processes added metal layers to handle growing routing density (Step 9), each new layer's topography compounded on top of the previous layers' unevenness, and by three to five metal layers, the accumulated topography could exceed the depth of focus of the lithography tools patterning the layers above it, risking out-of-focus, poorly resolved features on the upper layers regardless of how well the lower layers themselves were formed.

## 2. What Chemical-Mechanical Polishing Actually Does

Chemical-mechanical polishing (CMP) planarizes a wafer surface by pressing it, dielectric or metal side down, against a rotating pad soaked in a chemically active slurry, combining a mild chemical etching action with mechanical abrasion to remove material preferentially from raised areas faster than from recessed areas, converging the surface toward flat over the course of the polish. Unlike a purely mechanical lapping process or a purely chemical etch alone, the combination gives CMP a self-limiting, topography-dependent removal rate that neither mechanism achieves on its own, which is what makes it practical to planarize an entire wafer's surface to within the tight flatness tolerance multilevel lithography requires.

## 3. Two Distinct Jobs CMP Took On in Deep Submicron Flows

CMP planarizes interlevel dielectric between metal layers, restoring a flat surface for the next layer's lithography regardless of how uneven the metal pattern beneath it was — the job that directly solves the depth-of-focus problem described above. CMP also performs the tungsten-plug overfill removal Step 9 mentioned, polishing back the excess CVD tungsten deposited to fill contacts and vias, leaving tungsten only inside the holes and a flat surface everywhere else — a job the earlier blanket etch-back approach could do only roughly, with etch-back's own topography sensitivity limiting how well it worked as layer counts grew.

## 4. Why CMP Was a Prerequisite for the Copper Transition Pressure in Step 11

A damascene copper process, which fills pre-etched trenches with copper rather than etching a deposited copper blanket layer, inherently deposits a thick overburden of copper across the entire wafer surface that must be removed down to the trench tops, leaving copper only where the trenches were cut. CMP is the only practical way to perform that removal at the flatness and uniformity a multilevel damascene process needs, which is why CMP's maturation as a mainstream 1990s process step — initially adopted for dielectric planarization and tungsten-plug polish-back, exactly the jobs described above — is a direct enabling prerequisite for the copper interconnect transition, even though that transition itself lies just past this series' scope.