Hmos 1978 Step 16 SRAM Memory Applications Distinct Priorities

# Step 16 — Separate HMOS's Memory Applications From Its Logic Applications

## 1. Name the Second Product Line This Extension Has Not Yet Addressed

Every step of the base series and every step of this extension so far has reasoned about HMOS through a microprocessor's design priorities: a logic gate's switching speed, a ratioed inverter's current match, a flagship part's clock-speed competition against the Z8000 and 68000. Intel also built static RAM in the HMOS process — parts in the 2147/2148 family — and a memory cell's design priorities are not the same as a logic gate's, even though both are built from the same depletion-load NMOS devices on the same wafer. A logic gate is evaluated on propagation delay through a chain of gates with varying fan-in and fan-out, where the aspect-ratio tradeoff Step 3 of the base series worked out governs the whole design. A memory cell is evaluated on a narrower, more repetitive set of questions: can this exact cell, replicated several thousand times identically across the array, hold its stored state reliably, be read without disturbing that state, and be written and read fast enough to meet the part's access-time specification — all at the smallest possible cell area, because cell area multiplied by array size is nearly the entire die.

That narrower, more repetitive design target changes which of HMOS's process knobs matter most. Logic design in Steps 1 through 10 treated oxide thickness, implant dose, and channel length as levers to balance speed against power and reliability across a heterogeneous population of gates. Memory design treats the same levers as settings to be optimized once, for a single repeated cell, against a much tighter area budget than any individual logic gate faces.

Two Products, One Process, Different Design Targets the same depletion-load NMOS devices, optimized against different questions LOGIC (8086, Steps 1-10) heterogeneous gate population varying fan-in and fan-out evaluated on propagation delay through a chain of gates aspect ratio tuned per gate class to balance speed, power, reliability area budget shared across a diverse design MEMORY (2147/2148 SRAM) one cell, replicated thousands of times identical by design, not varied evaluated on state retention, read disturb, access time aspect ratio tuned once, for the single repeated cell cell area × array size is nearly the whole die SAME TRANSISTOR, DIFFERENT OPTIMIZATION TARGET everything Steps 1-10 established about the depletion-load device still applies — what changes here is which outcome the process's knobs are being tuned to produce

## 2. Show Where Memory's Priorities Diverge Concretely From Logic's

Read disturb is the clearest example of a question logic design never has to ask. A memory cell's stored state is read by sensing a small voltage or current difference on a bit line shared by every cell in that column; the act of reading must not itself change the state being read, which places a specific demand on the depletion-load pull-up's strength relative to the access transistor's — a current-matching question in the same family as Step 3's aspect-ratio tradeoff, but now constrained by a disturb margin that a logic gate's propagation-delay specification never imposes. A logic gate that marginally mis-sizes its load only runs slightly slower or faster; a memory cell that marginally mis-sizes its load can corrupt the bit it was asked to read, which is a correctness failure, not a performance one.

Access time is the second divergence. A logic chain's overall delay is the sum of many gate delays in series, so no single gate's speed dominates and small variances average out across the chain. A memory part's access-time specification is a single number governing the worst-case cell and worst-case bit-line path in the entire array, so the memory designer has to guarantee a speed floor across every one of several thousand nominally-identical cells, where the logic designer only had to guarantee an average across a much more heterogeneous population. This is why HMOS memory parts and HMOS logic parts, despite sharing the same underlying process technology documented across Steps 1 through 10, carried separate, specialized design rules and separate characterization procedures inside Intel — the process was common; the specification it had to meet was not.

Where a Mis-Sized Load Produces a Different Kind of Failure LOGIC GATE, MIS-SIZED LOAD runs somewhat slower or faster averages out across a long chain a performance degradation recoverable at the system timing level MEMORY CELL, MIS-SIZED LOAD read access can flip the stored bit no averaging across thousands of cells a correctness failure not recoverable after the fact SAME ASPECT-RATIO QUESTION FROM STEP 3, A STRICTER ANSWER REQUIRED memory inherited the depletion-load current-matching math and tightened its own margin, separate design rules inside Intel, same underlying process

## 3. Place This Step in the Extension's Own Lineage

This step does not add a new process trick to HMOS; it shows that the process documented across Steps 1 through 10 and the rest of this extension served two product families with genuinely different specifications, and that memory's disturb-margin and uniform-access-time requirements forced a specialized reading of the same depletion-load current-matching tradeoff Step 3 established for logic. Step 17 turns from Intel's own internal product split back to the external competitive landscape named in Step 11, specifically the second-source agreements that let other manufacturers build licensed or independently-engineered equivalents of Intel's HMOS parts — a commercial mechanism distinct from, but motivated by, the same clock-speed competition that opened this extension.

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