Hmos 1978 Step 20 Close Hmos Own Arc Historical Role

# Step 20 — Close HMOS's Own Arc on Its Own Terms

## 1. Gather What This Extension Added to the Base Series' Already-Complete Story

The base series' own Step 10 already classified what later microprocessor generations inherited from HMOS at the device-physics level: precision ion-implanted threshold tuning, aggressive gate-dielectric scaling, refractory-metal silicides, double-polysilicon routing, and a reliability discipline balancing oxide wearout against hot-carrier injection, set against a ratioed-logic topology and a rigid 5 V rail the industry eventually abandoned. This extension did not revisit that verdict or add a new device-physics finding to it. It filled in the business, equipment, economic, and application context around that verdict — the reasons HMOS existed in the form it did, not a different account of what it was physically.

Step 11 supplied the commercial motive the base series assumed without stating: Intel needed the 8086 clocked competitively against the Z8000 and 68000 without redesigning the industry's 5 V rail, and HMOS was the process that could deliver that on schedule. Step 12 supplied the equipment floor — 1978's contact-aligner tolerances — that bounded how much of Step 6's layout gain the process could actually bank. Steps 13 and 14 quantified two structural costs the base series only named in passing: static power, present whether the clock toggles or not, and a hot-carrier degradation rate specifically compounded by stacking a shorter channel on a thinner oxide at an unchanged voltage. Step 15 priced the yield consequence of the second-polysilicon flow Step 6 introduced. Step 16 showed the same process serving a second product family, memory, under a different and stricter specification. Steps 17 through 19 followed the commercial and manufacturing threads outward — second-sourcing, packaging, and speed-grade binning — showing that a device-level engineering decision keeps generating consequences long after the transistor itself is finished.

Ten Steps Filling in the Context Around an Already-Complete Verdict Steps 1-10 answered what HMOS was physically; Steps 11-20 answer why, at what cost, and to what end STEPS 1-10 (BASE SERIES): fixed-voltage scaling, depletion load, oxide thinning, poly 2, clock payoff, HMOS-II, CMOS comparison, inheritance COMMERCIAL (11, 17, 19) why Intel chose this path second-source market access binning monetizes variability PHYSICAL COST (13, 14, 18) static power quantified compounded hot-carrier rate packaging absorbs the heat MANUFACTURING (12, 15, 16) 1978 alignment tolerance second-poly yield economics logic vs. memory specifications NOTHING HERE REVISES THE BASE SERIES' DEVICE-PHYSICS VERDICT Step 10's taxonomy of inherited foundations and abandoned paradigms stands exactly as it was — this extension explains the surrounding decisions, costs, and consequences that made that physics matter a fuller account of the same device, not a different one

## 2. State What HMOS Was, Honestly, Without Reaching for a Forced Successor

HMOS was a process engineering achievement bounded, from the start, by a voltage rail it was never going to be allowed to change and a ratioed-logic topology it was never going to escape without abandoning the device family its own customers already depended on. Within those two fixed boundaries, Steps 1 through 10 and this extension together document a genuinely difficult, genuinely successful piece of engineering: a roughly fourfold gain in clock speed and power-delay product, achieved without breaking compatibility with a single existing board, delivered on a schedule competitive against Zilog and Motorola, sold through a second-source structure that satisfied systems customers' supply-risk requirements, packaged to survive the power it drew, and binned to extract full commercial value from the process variability it could not eliminate. That is HMOS's own, complete historical role, independent of whatever came after it.

What came after it is already told, at length, elsewhere in this knowledge base. The static power this extension quantified in Step 13 is exactly the term the `cmos_logic_1980s` and `cmoscrossover_1980` series document crossing the line NMOS could no longer defend, as those series' own power accounting makes explicit against HMOS-II's specific numbers. This extension does not retell that displacement, because it is not HMOS's story to tell — it is the story of what replaced HMOS, told from the replacement's own point of view, and duplicating it here would blur a boundary this project has otherwise kept clean throughout. HMOS's arc closes on its own achievement and its own honestly-documented limits, the same way the Micrologic 1960 and Epitaxial 1961 extensions closed before it: open-ended, without a single named successor forced onto a series that does not need one to be complete.

HMOS's Own Closed Arc, Beside the Story Told Elsewhere HMOS'S OWN COMPLETE STORY (THIS SERIES) fixed-voltage scaling constraint (Step 1) depletion load, oxide, poly 2 (Steps 2-6) measured payoff, HMOS-II limit (Steps 7-9) inheritance taxonomy (Step 10) commercial motive, equipment floor, static power, reliability, yield, memory, second-source, packaging, binning (Steps 11-19) complete, closed, on its own terms THE DISPLACEMENT STORY (TOLD ELSEWHERE) cmos_logic_1980s series cmoscrossover_1980 series static power crossing the line HMOS-II margin test, specifically power-delay-density comparison what later CMOS inherits named by reference here, not retold two series, two points of view, one boundary this project keeps clean HMOS's extension ends here, without manufacturing a handoff it does not need

## 3. Final Placement

This step closes the `hmos_1978` extension at step 20. It adds no device-physics finding beyond what the base series' own Step 10 already established, and it names, without retelling, the separate `cmos_logic_1980s` and `cmoscrossover_1980` series that document NMOS's displacement from HMOS's own static-power term outward. The extension's own contribution is the business, equipment, economic, and application context in Steps 11 through 19: why Intel built HMOS the way it did, what it actually cost to build and operate, and how the same process served two distinct product families under two distinct specifications. HMOS closes here as a complete, historically honest account of a difficult engineering achievement bounded by constraints it was never going to escape — not as a staging post toward a successor this series does not need to name to be finished.

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