Human Body Model (HBM)

Human Body Model testing is the oldest and still most widely required ESD qualification for integrated circuits, built around a deliberately simple idea: model a person who has picked up a static charge and then touches a pin of a device. The stress network stores charge on a 100 pF capacitor representing body capacitance, then discharges that capacitor through a 1.5 kΩ resistor representing the resistance of a human arm and hand into the device under test, one pin or pin-combination at a time. Because the network is so simple, the resulting current waveform is almost entirely predictable from first-order circuit theory, which is exactly why HBM has remained the anchor ESD model for qualification even as newer models such as Machine Model and Charged Device Model were introduced to cover threat scenarios that HBM does not represent well. Component-level HBM testing traces back decades of qualification history, and its persistence as a baseline requirement, alongside newer models rather than instead of them, reflects how much accumulated field data and process-design-kit correlation now depends on the same 100 pF and 1.5 kΩ reference network.

The HBM discharge produces a double-exponential current waveform whose shape is set almost entirely by the RC time constant of the test network rather than by the device under test. A fast leading edge, nominally around 1 ns, is followed by a slower decay with a time constant near 150 ns, so that the bulk of the stress energy is delivered within roughly the first 700 ns of the pulse. Because the 100 pF capacitor and 1.5 kΩ resistor dominate the waveform, two different HBM testers using the same nominal component values should, in principle, produce nearly identical current pulses on a resistive load, which is what makes HBM results comparable across test houses and qualification labs. Peak current scales roughly linearly with stress voltage on a fixed resistive load, so an 8000 V stress event drives substantially more current through the device than a 2000 V event even though both share the same 1 ns rise and 150 ns decay shape.

Stress levels are organized into JEDEC HBM classes that map directly onto how carefully a component must be handled on the factory floor. Class 0 parts fail below 250 V and require the strictest ESD control available, Class 1A through 1C parts fail somewhere between 250 V and 2000 V and still demand disciplined handling, while Class 2 parts surviving 2000 V to 4000 V and Class 3A/3B parts surviving 4000 V to 8000 V can tolerate baseline handling procedures without exotic precautions. A single classification number therefore compresses an entire chain of packaging, shipping, and assembly-line decisions into one comparable figure that a factory floor can act on without re-deriving the underlying physics. Modern process nodes with thinner gate oxides and smaller junction areas have pushed many designs toward the lower classes, which is one reason on-chip ESD protection circuitry has grown more, not less, important as transistor dimensions shrink.

Rise time is not solely a property of the stress network; it is also shaped by parasitic inductance in the test socket, cabling, and fixture, which is why HBM testers are calibrated against a reference waveform rather than trusted on nominal component values alone. Excess parasitic inductance rounds off the leading edge and can shift the apparent peak current lower or later in time, which in turn can make a marginal device appear to pass when a better-calibrated fixture would have failed it. Waveform verification at each stress voltage, checking rise time, peak current, and decay time constant against a reference envelope, is therefore mandatory before any qualification data from a given tester is considered valid. Verification is typically repeated at several voltages spanning the full 250 V to 8000 V range rather than trusted at a single calibration point, since inductive rounding does not scale linearly with stress amplitude.

Failure and leakage criteria for HBM qualification are defined around parametric shift rather than catastrophic failure alone, since a device that still functions but has drifted well outside its datasheet limits has effectively failed in the field. A common criterion allows no more than a modest percentage change, often on the order of a 10% shift, in a defined set of leakage or parametric measurements between the pre-stress and post-stress characterization steps, with any device exceeding that threshold classified as a failure regardless of whether it still powers on. Positive and negative pulses are applied to every required pin combination, and a device must pass all of them at a given voltage to earn that classification level. A device that passes 2000 V but fails at 4000 V is simply reported at its highest passing class rather than treated as a marginal or borderline result, since HBM classification is a discrete pass bar rather than a continuous score.

HBM correlates reasonably well with real-world handling events such as a technician touching a board edge connector, but it correlates poorly with the much faster, higher-current discharge that occurs when a charged package itself dumps its own stored charge through a single pin, which is the domain of the Charged Device Model. Machine Model, in turn, represents a charged tool or fixture discharging into a device with near-zero series resistance, producing an oscillatory waveform quite different from either HBM or CDM. Because each model captures a different physical threat, qualification programs typically require passing scores against more than one model rather than treating HBM performance as a complete picture of ESD robustness. A device with a comfortable Class 2 HBM rating near 3000 V can still fail a CDM test at a fraction of that nominal voltage, since CDM stresses a completely different discharge path and time scale.

Post-stress failure analysis closes the loop between an HBM pass/fail number and the physical mechanism that actually failed, since two devices can fail the same voltage class for entirely different reasons. AFM topography reveals localized surface damage or metallization deformation at a suspected failure site, SIMS depth profiling checks for contamination or dopant redistribution near a ruptured oxide, XPS confirms the chemical state of exposed surfaces after a failure event, and DLTS spectroscopy characterizes trap states introduced into the gate oxide or junction by the stress pulse. Electrical confirmation runs on Keithley source-measure units referenced to NIST-traceable standards, while Keysight pulse generators and oscilloscopes verify that the applied waveform itself met the calibration envelope before any failure is attributed to the device rather than the test setup. Four-point probe measurements of local sheet resistance can also reveal metallization thinning near a stressed bond pad that would otherwise be missed by a purely electrical pass/fail check.

Select device and pin map → Pre-stress parametric characterization → Charge 100 pF network to target voltage → Discharge through 1.5 kΩ into DUT (positive and negative, all pin combinations) → Post-stress parametric characterization → Compare shift against pass/fail criteria → Assign JEDEC HBM class → Failure analysis on rejected units (AFM, SIMS, XPS, DLTS)

Viewed through an ESD-robustness qualification lens, the Human Body Model reduces a messy real-world event, a charged person touching a pin, into a fully specified RC circuit with a 100 pF capacitor, a 1.5 kΩ resistor, a roughly 1 ns rise time, and a roughly 150 ns decay, and it is precisely that reduction to a repeatable, calibratable waveform that has kept HBM at the center of ESD qualification even as Machine Model and Charged Device Model testing were added to cover the threats HBM was never designed to represent.