iddq testing

**IDDQ Testing** is a **test methodology that measures the quiescent (steady-state) power supply current** — of a CMOS IC when it is in a stable, non-switching state. A defect-free CMOS circuit should draw near-zero static current; elevated IDDQ indicates a defect. **What Is IDDQ Testing?** - **Principle**: In defect-free CMOS, the only current path from VDD to GND is through leakage. This should be nanoamps. - **Defect Indicator**: A gate oxide short, bridging fault, or stuck-open fault creates a direct current path -> microamps or milliamps. - **Procedure**: Apply a test vector -> Wait for circuit to settle -> Measure $I_{DDQ}$. **Why It Matters** - **Bridging Fault Detection**: IDDQ is the gold standard for detecting resistive shorts that logic testing misses. - **Reliability Screening**: Chips with elevated IDDQ (even if they pass logic tests) are likely to fail in the field (latent defects). - **Challenge**: As process nodes shrink (7nm, 5nm), background leakage increases, making defect-induced current harder to distinguish. **IDDQ Testing** is **the blood pressure check for chips** — detecting hidden internal defects by measuring abnormal power consumption at rest.