semiconductor test

**Semiconductor Production Testing** is the **manufacturing discipline that verifies every die on every wafer meets functional and parametric specifications — using automated test equipment (ATE) that executes billions of test vectors per second while measuring voltage, timing, current, and frequency parameters, where test time directly determines per-die cost and any escape (defective die reaching the customer) can result in field failure, product recall, and reputational damage**. **Test Flow** 1. **Wafer Probe (Wafer Sort)**: Before dicing, a probe card contacts every die on the wafer through bond pads. Basic functional tests and parametric measurements identify good/bad dies. Bad dies are inked or mapped for exclusion during packaging. Test time: 0.1-2 seconds per die. 2. **Package Test (Final Test)**: After dicing and packaging, each packaged device undergoes comprehensive testing. Functional tests at multiple voltage/temperature corners. Test time: 1-30 seconds for complex SoCs. 3. **Burn-In**: Stress testing at elevated temperature (125°C) and voltage (10-20% above nominal) for hours to accelerate infant mortality failures. Increasingly replaced by voltage/temperature screening at final test for cost reduction. 4. **System-Level Test (SLT)**: Device boots and runs application-level workloads in a socket that simulates the end system. Catches defects invisible to structural tests. Used for high-reliability automotive and data center parts. **Design for Testability (DFT)** - **Scan Chains**: Flip-flops are connected into shift registers that allow direct observation and control of internal logic state. ATPG (Automatic Test Pattern Generation) tools compute test vectors that detect >99% of stuck-at, transition, and bridge faults. - **BIST (Built-In Self-Test)**: On-chip test logic for memories (MBIST), PLLs (ABIST), and I/O interfaces. Reduces ATE pin requirements and enables at-speed testing. - **Boundary Scan (JTAG)**: IEEE 1149.1 standard for testing inter-chip connections at the board level. Flip-flops at every I/O pin enable controllability and observability of board-level interconnects. - **Compression**: Test data compression (e.g., Synopsys DFTMAX, Cadence Modus) reduces the data volume by 10-100x, cutting test time proportionally. **Test Economics** - **ATE Cost**: A modern digital ATE system (Advantest V93000, Teradyne UltraFLEX) costs $5-15M. A mixed-signal ATE system costs $10-25M. - **Test Time = Cost**: At $0.01-0.05 per second of ATE time, a complex SoC tested for 10 seconds costs $0.10-0.50 in test cost alone. Multiplied by millions of units, test cost optimization is critical. - **Adaptive Test**: ML models trained on inline data predict which dies are likely defective, enabling longer test times for suspicious dies and shorter times for likely-good dies — reducing average test time by 20-40% without increasing escapes. Semiconductor Production Testing is **the quality gateway between fabrication and the customer** — the final manufacturing step that ensures every chip performs correctly, determining both the cost structure and the reliability reputation of the semiconductor product.