semiconductor test burn-in

**Semiconductor Test and Burn-In** is **the comprehensive set of electrical verification and stress screening procedures applied at wafer-level and package-level to detect manufacturing defects, infant mortality failures, and parametric outliers before shipping to customers, ensuring quality levels below 1 DPPM for automotive and mission-critical applications**. **Wafer-Level Testing (Wafer Probe):** - **Probe Card Technology**: cantilever, vertical, or MEMS probe cards contact die bond pads (50-80 µm pitch) with 100-10,000+ probe tips simultaneously; probe tip material typically tungsten or palladium alloy - **Probe Temperature**: testing at multi-temperature (−40°C, 25°C, 105°C or 125°C) screens speed-path failures and leakage outliers across operating range - **Test Coverage**: functional test patterns exercise 60-80% of transistors; scan-based structural tests (stuck-at, transition, path delay) achieve >98% fault coverage - **Test Time**: typical SoC wafer probe test time 2-10 seconds per die; memory devices 0.5-2 seconds per die; test time directly impacts cost ($0.01-0.10 per die for commodity, $1-10 for complex SoCs) - **Multisite Testing**: modern ATE (automatic test equipment) tests 8-128 die simultaneously to amortize tester cost; Advantest V93000, Teradyne UltraFlex platforms **Structural Test Methodologies:** - **Scan Test**: flip-flops connected in scan chains allow shift-in of test patterns and shift-out of results; stuck-at fault model with >99% coverage; transition fault test detects timing-related defects - **IDDQ Testing**: measures quiescent power supply current; healthy CMOS circuit draws <1 µA quiescent; defective circuits with bridging faults draw 10-1000 µA; effective at detecting gate oxide defects and metal shorts - **Built-In Self-Test (BIST)**: on-chip test pattern generation and response analysis for memories (MBIST), logic (LBIST), and I/O interfaces—reduces external tester requirements - **ATPG (Automatic Test Pattern Generation)**: software tools (Synopsys TetraMAX, Cadence Modus) generate compact test pattern sets maximizing fault coverage from gate-level netlist **Burn-In Screening:** - **Purpose**: accelerated stress at elevated voltage (V_DD + 10-20%) and temperature (125-150°C) for 24-168 hours precipitates infant mortality failures—removes early-life failures from the bathtub curve reliability distribution - **Static Burn-In**: device powered at elevated voltage/temperature without exercising logic; stresses gate oxide (TDDB) and metallization (electromigration) - **Dynamic Burn-In**: device operated with functional or scan test patterns during stress; toggles transistors to stress both static and dynamic failure mechanisms - **Burn-In Board**: specialized PCB holds 32-256 devices in sockets with independent power supply monitoring and thermal management - **HTOL (High Temperature Operating Life)**: qualification-level accelerated life test at 125°C, V_DD_max for 1000+ hours—extrapolates to 10-year field lifetime using Arrhenius and Eyring models **Known-Good-Die (KGD) Testing:** - **Challenge**: bare die destined for multi-chip module (MCM), 2.5D, or 3D integration must be fully tested before assembly—rework of assembled multi-die packages is prohibitively expensive - **Wafer-Level Burn-In (WLBI)**: performs burn-in stress at wafer level before singulation; emerging for HBM and advanced packaging applications - **Temporary Bonding**: test chip mounted temporarily for full-speed functional testing, then singulated for assembly—adds cost but ensures KGD quality **Test Economics and Optimization:** - **Cost of Test**: semiconductor test cost represents 5-15% of total manufacturing cost; reducing test time by 10% saves millions annually in high-volume production - **Adaptive Testing**: machine learning algorithms analyze inline parametric data to predict which die need full testing vs abbreviated screening—reduces test time 20-40% for known-good wafer lots - **Test Escape Rate**: target <1 DPPM (defective parts per million) for automotive; <10 DPPM for consumer; achieved through complementary test methods (scan + IDDQ + functional + burn-in) - **Yield Learning**: test data analytics identify systematic yield limiters; Pareto analysis of fail bins drives process improvement feedback to fab **Semiconductor test and burn-in represent the final quality gate before products reach customers, where the combination of structural testing, functional verification, and accelerated stress screening must achieve near-zero escape rates while maintaining economically viable test times in an industry where quality expectations continue to tighten with every application generation.**