Ccd Potential Well Charge Transfer

# CCD's Walking Potential Well vs. CMOS's Direct Address

two different answers to reading a million-point grid through a handful of pins

CCD — CHARGE WALKS THE POTENTIAL WELL three clock phases, same charge packet, three moments in time t₁ — φ1 high, charge sits under electrode 1 Q φ1 φ2 t₂ — φ2 rises, φ1 falls: well shape tilts, charge spills forward Q φ1 φ2 ↑ t₃ — φ2 high, φ1 off: charge now fully under electrode 2 Q φ2 φ3 one well-hop per clock cycle repeat this hop across the whole row — every pixel's charge rides the same conveyor to one corner amplifier a single, carefully-matched amplifier reads every pixel → very uniform, very low noise but nothing can be read until its charge has walked the entire distance → serial bottleneck Boyle & Smith, Bell Labs, 1969 — conceived as a memory device, not an imager

Backside illumination later undid CMOS's one real cost — wiring blocking light — by thinning the wafer and letting photons enter from behind it entirely.

CMOS's direct-address wiring, not a physics advantage in light capture, is what let it absorb on-chip ADC, in-pixel amplification, and eventually nearly all volume imaging.

SERIAL CONVEYOR vs. DIRECT ADDRESS same 4×4 pixel grid, two different ways out CCD A one amplifier — every charge travels here first CMOS row-select + column-read — every pixel exits on its own line this is why CMOS supports rolling AND global shutter, while CCD only supports one global pattern each CMOS pixel carries its own amplifier (3T/4T) — lower per-pixel noise match, but more silicon per pixel Eric Fossum, JPL, early 1990s active-pixel sensor: put the amplifier at every site, not just at the end of the conveyor later: on-chip ADC + signal processing became the integration edge

CCD persists today only in a handful of scientific/medical niches — this is the project's first imaging-class series, beside memory and power

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