in-memory

**In-Memory Computing Resistive Arrays** is **performing computation directly in memory arrays by exploiting resistive device properties (analog conductance), enabling massive parallelism and energy efficiency** — transcends von Neumann bottleneck. In-memory computing merges storage and compute. **Resistive Devices** resistive RAM (RRAM), phase-change memory (PCM), memristors. Conductance G (0 to G_max) analog value. G = G_min + ΔG*(state), where state continuously varies. **Memristors** two-terminal devices: resistance depends on charge history. V-i characteristic hysteretic. Analog conductance enables computing. **RRAM (ReRAM)** filamentary conduction: metal filament forms/ruptures between electrodes. Conductance state (0 = off, 1 = on) or intermediate. **Phase-Change Memory (PCM)** material transitions amorphous (high resistance) ↔ crystalline (low resistance). Intermediate states possible. Used in Intel Optane. **Crossbar Arrays** devices arranged in array: rows and columns form matrix. Vector-matrix multiply: V_out = R⁻¹ * V_in. **Vector-Matrix Multiplication** fundamental to neural networks. Y = W·X (matmul). Implement via resistive array: X input voltages, W stored as conductances, Y output currents. **Analog Domain Computation** currents naturally sum via Kirchhoff's law. Summation native to crossbar. **Neural Network Acceleration** map neural network weights to conductances. Forward pass: matrix multiply via crossbar. Parallel across array. **ADC/DAC Overhead** inputs analog: require DAC. Outputs analog currents: require ADC/integrate-accumulate. Overhead limits gain. **Precision Tradeoffs** analog computation: noisy, limited precision (~4-8 bits practical). Quantization-aware training tolerates. **Programming Precision** writing conductance G requires control. Multi-level programming: intermediate pulses. Precision ~16 levels typical. **Variability and Drift** device conductance varies (conductance variability) and drifts over time (temporal drift). On/off ratio changes. Algorithms tolerate via calibration. **Noise Sources** shot noise (poisson), flicker noise, programming noise. **Conductance Levels** digital: 0 or 1. Analog: continuous 0-G_max. More levels increase computation density. **Multi-Bit Encoding** store multiple bits per device via multi-level conductance. More bits denser but lower SNR. **Hybrid Approaches** analog crossbar computation + digital post-processing. Reduce ADC/DAC precision. **Systolic Arrays** systolic processors (TPUs) use dataflow for matrix multiply. Different parallel architecture. **Mapping to Resistive Arrays** neural networks layer-by-layer: each layer → one crossbar. Inter-layer: convert output current to voltage (transimpedance amp), digitize, next layer. **Update Mechanisms** learning requires weight updates (backpropagation gradients). Update via write pulses: increase/decrease conductance. Analog update on-array. **Online Learning** compute updates on-chip, immediately apply. No off-chip gradient computation. **Sparsity Exploitation** sparse networks: zero conductances consume no power, occupy space. Sparsity-aware design. **Temperature Compensation** device properties (G, on/off ratio) drift with temperature. Compensation circuits adjust. **3D Arrays** stack crossbars vertically: increase array density. Interconnect between layers. **Testability and Yield** crossbars sensitive to failures (stuck-off/stuck-on devices). Testing, repair important. Yield lower than standard silicon. **Comparison with Digital Accelerators** in-memory: high throughput density, low precision, analog noise. Digital: lower density, higher precision, noise-free. **Neuromorphic Chips with Analog** neuromorphic + in-memory computing: combine spiking neuron efficiency with analog computation. **Commercial Development** IBM, Mythic, Analog Inference developing. **Challenges** manufacturing variability, calibration complexity, thermal management. **Applications** neural network inference (edge AI), optimization problems (quadratic programming), scientific computing. **In-memory computing paradigm enables massive parallelism** at energy efficiency beyond digital approaches.