integrated clock gating cell (icg)
**An Integrated Clock Gating cell (ICG)** is a **specialized standard cell** that combines a **latch, AND gate, and clock buffer** into a single optimized cell — providing glitch-free clock gating to disable the clock to idle flip-flops, which is the most effective technique for reducing dynamic power in synchronous digital designs.
**Why Clock Gating?**
- In a typical design, most flip-flops don't toggle every clock cycle — many hold their value while waiting for new data.
- Without clock gating, the clock still toggles at every flip-flop every cycle — wasting power on unnecessary switching.
- **Clock gating** disables the clock to idle flip-flops — saving the switching power of both the flip-flop and the clock tree driving it.
- Clock gating can reduce total dynamic power by **20–50%** — the single largest power reduction technique.
**ICG Cell Architecture**
- **Enable Latch**: An active-low latch that captures the enable signal on the clock's inactive edge — preventing glitches when the enable signal changes during the active clock phase.
- **AND Gate**: Gates the clock with the latched enable — when enable is low, the output clock is held inactive (low for positive-edge systems).
- **Clock Buffer**: Drives the gated clock output with adequate strength for the downstream fanout.
**Why Not a Simple AND Gate?**
- Gating the clock with a raw AND gate (clock AND enable) creates **glitches** if the enable signal changes while the clock is high — the output can produce short spurious pulses that cause flip-flop errors.
- The latch in the ICG ensures the enable signal is only sampled when the clock is low (for positive-edge clocking) — any enable transitions during clock high are ignored.
- This makes the gated clock **glitch-free** — essential for reliable operation.
**ICG in the Design Flow**
- **RTL Insertion**: Clock gating is typically inferred by the synthesis tool from RTL patterns like:
```
if (enable) register <= data;
```
The tool recognizes the conditional load and inserts an ICG cell.
- **Synthesis Control**: Minimum number of flip-flops to justify an ICG insertion (e.g., 4–8 flip-flops minimum — the ICG cell itself has area and power cost).
- **Hierarchical Gating**: Multiple levels of clock gating — top-level gates disable entire modules, lower-level gates disable individual registers.
- **Physical Design**: ICG cells are placed close to their flip-flop clusters to minimize gated clock wire length.
**ICG Cell Variants**
- **Standard ICG**: Enable + clock → gated clock. Most common.
- **ICG with Test Enable**: Additional test_enable input that bypasses the gating during scan testing — ensures all flip-flops receive the clock during test.
- **ICG with Set/Reset**: Additional control for initialization.
**Power Impact**
- Each ICG cell saves: $P_{saved} = N_{FF} \cdot C_{clk} \cdot V_{dd}^2 \cdot f \cdot \alpha_{idle}$
Where $N_{FF}$ is the number of gated flip-flops, $\alpha_{idle}$ is the fraction of time they're idle.
- A well-gated design can have **60–80%** of its flip-flops gated at any given time — massive power savings.
The ICG cell is the **cornerstone of low-power digital design** — it is the single most important standard cell for power reduction, found in virtually every modern chip.