interconnect delay

Interconnect delay is the signal propagation delay through metal wires, dominated by the RC time constant of resistance and capacitance, which has become the primary speed limiter at advanced nodes. Physics: delay ∝ R × C, where R = ρL/(W×H) (wire resistance) and C = εL×H/S (coupling capacitance). As pitch shrinks, R increases (smaller cross-section + scattering effects) and C increases (tighter spacing). Delay components: (1) Intrinsic wire delay—RC of the wire itself; (2) Driver delay—gate driving wire load; (3) Receiver delay—input capacitance of receiving gate. Delay models: (1) Lumped RC—simple R×C product; (2) Elmore delay—distributed RC tree model; (3) Reduced-order models—AWE, PRIMA for complex networks; (4) Full extraction—parasitic extraction (PEX) with detailed 3D field solving. Historical crossover: at 180nm node, gate delay dominated; by 90nm, interconnect delay exceeded gate delay; at 7nm and below, interconnect delay is 2-5× gate delay. Mitigation strategies: (1) Low-κ dielectrics—reduce C (SiOCH, air gaps); (2) New metals—Co, Ru for lower R at small dimensions; (3) Repeater insertion—break long wires with buffers; (4) Wire sizing—wider wires for critical nets; (5) Metal layer assignment—use thicker upper metals for global signals; (6) Architectural—pipeline stages to limit wire length; (7) 3D integration—shorten vertical connections. Design impact: timing closure increasingly constrained by routing, placement must minimize wirelength on critical paths. Signal integrity: RC delay interacts with crosstalk (coupling capacitance), making timing analysis more complex. Interconnect delay drives both BEOL material innovation and architectural design choices at every advanced node.