via resistance

**Via Resistance** is the **electrical resistance of the conductive plug connecting two metal layers** — a critical parameter that increases as via dimensions shrink, contributing to the overall RC delay of the interconnect stack. **What Determines Via Resistance?** - **Components**: $R_{via} = R_{Cu-fill} + R_{barrier} + 2 imes R_{contact}$ (top and bottom landing). - **Cu Fill**: $R = ho L / A$. As via diameter shrinks, area drops quadratically. - **Barrier**: The TaN/Ta barrier takes up a significant fraction of the via cross-section at small diameters. - **Contact Resistance**: Interface resistance between via and metal line (depends on cleanliness and barrier quality). **Why It Matters** - **Scaling Crisis**: At via diameters < 20 nm, barrier metal occupies > 50% of the cross-section, dramatically increasing resistance. - **Circuit Impact**: High via resistance increases IR drop and slows signal propagation. - **Solutions**: Thinner barriers, new barrier materials (Ru, Co), and barrierless via fills. **Via Resistance** is **the toll booth between metal layers** — a resistance penalty that gets increasingly expensive as interconnect dimensions shrink.