interposer

An interposer is a thin routing layer — usually silicon — placed between one or more dies and the package substrate, so that dies with very fine connections can talk to each other across a single package. It is the foundation of 2.5D integration: instead of stacking chips vertically, you set them side by side on the interposer and let it carry the dense wiring between them.\n\n**It bridges a fine-pitch die world to a coarse-pitch board.** A modern die has bump pitches measured in microns; an organic package substrate is far coarser. A silicon interposer, patterned with the same back-end-of-line tools as a chip, can route thousands of micron-pitch wires (its redistribution layers, RDL) directly between neighboring dies. Through-silicon vias then pass power and slower I/O straight down through the interposer to the substrate, and C4 bumps and BGA balls take it out to the board.\n\n**This is what lets a GPU sit next to its HBM.** Placing a logic die and one or more HBM stacks on a shared interposer gives them a very wide, very short electrical path — thousands of parallel connections only millimeters long. That is exactly the high-bandwidth, low-energy link an accelerator needs to feed its compute, and it is why 2.5D-on-interposer packaging (TSMC's CoWoS being the best-known example) became the standard way to build AI accelerators. The interposer is the wiring plane; the dies are the tenants.\n\n| Layer | Pitch | Role |\n|---|---|---|\n| Die bumps | micron-scale | connect die to interposer |\n| Interposer RDL | micron-scale | dense die-to-die routing |\n| Interposer TSV | — | power & I/O down to substrate |\n| C4 bumps | ~100 um | interposer to substrate |\n| BGA balls | ~mm | package to board |\n\n```svg\n\n```\n\n**The tradeoff is area, cost, and reticle size.** A silicon interposer is essentially a large, passive chip, so it is expensive and — because it must span multiple dies — it can exceed the lithography reticle limit, forcing stitching or bridge alternatives. Cheaper options trade some routing density for cost: silicon bridges (EMIB) embed a small piece of silicon only where dense routing is needed, and RDL/fan-out interposers use organic layers. The choice is always routing density and bandwidth versus area cost and manufacturability.\n\nRead the interposer through a quant lens rather than a 'carrier' lens: what matters is die-to-die bandwidth density (wires per mm of die edge), the energy-per-bit of that short hop, and the interposer area you must buy to get it. Per the roofline, the interposer is where an accelerator's HBM bandwidth is physically wired, so the design question is how many micron-pitch connections you can route and how large a slab that requires — a measured density-versus-cost trade, not a free substrate.