silicon interposer
**Silicon Interposer and 2.5D Integration** is the **advanced packaging technology that places multiple chiplets side-by-side on a passive silicon substrate containing through-silicon vias (TSVs) and ultra-fine metal redistribution layers** — enabling die-to-die connections with 1–10 µm pitch that achieve bandwidth densities 100× higher than conventional organic package substrates, allowing chipmakers to assemble heterogeneous systems combining logic dies, HBM memory stacks, and specialty chips from different foundry nodes.
**Why 2.5D vs Monolithic**
- Monolithic SoC at leading node: Die area → yield falls exponentially (Bose-Einstein yield model).
- 2.5D disaggregation: Split into smaller chiplets → each dies at high yield → better economics.
- Heterogeneous nodes: Logic at 3nm, cache at 5nm, analog at 16nm → optimize each for best node.
- Reusability: Same HBM die + different compute dies → product differentiation.
**CoWoS (Chip-on-Wafer-on-Substrate) — TSMC**
- CoWoS-S (Silicon): Full silicon interposer → 65µm TSV pitch, RDL down to 0.4µm L/S.
- CoWoS-R (RDL): Organic RDL interposer → cheaper, larger, less fine-pitch.
- CoWoS-L (Local): Localized silicon bridge embedded in organic substrate → hybrid.
- Applications: NVIDIA H100 (HBM3 + GPC chiplets on CoWoS-S), AMD MI300X.
**Interposer Specifications**
| Feature | Organic PCB | Organic Interposer | Silicon Interposer |
|---------|------------|-------------------|-------------------|
| Line/Space | 10–50 µm | 2–5 µm | 0.4–2 µm |
| TSV diameter | N/A | N/A | 5–10 µm |
| Die-to-die bandwidth | Low | Medium | Very High |
| Cost | Baseline | 1.5–2× | 3–5× |
| Thermal resistance | Low | Medium | High (Si is good) |
**TSV (Through-Silicon Via) in Interposer**
- Deep Bosch etch → TSV depth 50–100 µm, diameter 5–10 µm → AR 5–15:1.
- Liner: SiO₂ (insulation) → barrier: TaN/Ta → Cu fill (electroplating).
- TSV density: 1,000–10,000 TSVs/mm² → enables vertical HBM stack connections.
- Stress: Cu TSV has different CTE than Si → thermal cycling stress → keep-out zones required around TSVs.
**HBM + GPU Integration on CoWoS**
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**UCIe (Universal Chiplet Interconnect Express)**
- Open standard for die-to-die interface on advanced packages.
- Advanced package tier: 2 µm bump pitch → 16 Tbps/mm².
- Standard package tier: 25 µm bump pitch → 1.3 Tbps/mm².
- Supports PCIe/CXL protocol layer over physical UCIe layer.
**Thermal Challenges**
- Silicon interposer has good thermal conductivity (150 W/m·K) but adds thickness.
- Multiple stacked dies + interposer → thermal resistance stack increases.
- Liquid cooling increasingly required for 300-600W GPU packages.
Silicon interposer and 2.5D integration are **the packaging innovation that enabled the AI compute revolution at scale** — by allowing NVIDIA to place 80GB of HBM3 memory with 3.35 TB/s bandwidth directly adjacent to the GPU die on a silicon interposer, CoWoS technology bypasses the memory bandwidth wall that would have limited AI training throughput, making modern AI training clusters physically possible and driving unprecedented demand for advanced packaging capacity that has become a key semiconductor supply chain constraint.