Redistribution Layer Rdl

# Redistribution Layer (RDL) Technology: Fabrication, Pitch Scaling & High-Frequency Physics

In advanced semiconductor packaging and heterogeneous integration, a Redistribution Layer (RDL) is a high-density planar wiring network composed of thin-film copper conductors and low-k dielectric polymers. Its primary function is to redistribute the ultra-dense, sub-micron input/output (I/O) pad arrays of advanced silicon dies to relaxed pitches suitable for solder micro-bumps, flip-chip C4 spheres, silicon interposers, or package ball grid arrays (BGAs).

RDL technology is the foundational interconnect architecture across 2.5D and 3D multi-die platforms, including Fan-Out Wafer-Level Packaging (FOWLP) (e.g., TSMC InFO, ASE FoCoS), high-density organic substrate bridges (e.g., Intel EMIB), and high-bandwidth memory (HBM) base dies. As monolithic system-on-chips (SoCs) disaggregate into multi-chiplet topologies, RDL performance governs critical inter-die parameters: line resistance, parasitic capacitance, propagation delay ($\tau = RC$), signal crosstalk, and high-frequency insertion loss at millimeter-wave frequencies ($> 28\text{ to }112\,\text{GHz}$).

Semi-Additive Process (SAP) & Seed Etch Undercutting six-step fabrication sequence and the physical undercutting scaling limit at fine line/space pitches SEMI-ADDITIVE PROCESS (SAP) FLOW 1. Dielectric Coating & Via Lithography: Spin-coat Photosensitive Polyimide (PSPI) or PBO (3–5 μm). UV i-line expose & develop blind micro-vias. 2. PVD Barrier & Seed Sputtering: Sputter 30–50 nm Titanium (Ti) adhesion/diffusion barrier. Sputter 150–300 nm Copper (Cu) conductive seed layer. 3. Dry-Film Photoresist Patterning: Laminate thick negative photoresist (5–10 μm). Direct-write laser lithography opens fine trace trenches. 4. Electrolytic Copper Electroplating: Bottom-up acid Cu electroplating with organic additives. Deposits 2–5 μm high-purity Cu in trenches & micro-vias. 5. Resist Strip & Differential Seed Etch: Solvent strip photoresist, exposing background seed layer. Wet chemical flash etch removes seed Cu & barrier Ti. Key SAP Advantages: • Vertical sidewall profile (aspect ratio AR > 1:1) • Highly scalable for 2/2 μm to 5/5 μm Line/Space routing • Compatible with large 300 mm wafers and 510×515 mm panels • Multi-layer stacking: up to 4–6 RDL routing layers SEED ETCH UNDERCUTTING MECHANICS Underlying Dielectric (Polymer / SiO₂) Electroplated Cu (Thickness t = 2–3 μm) Nominal Width w = 2.0 μm Undercut δ_u ~0.2–0.3 μm The SAP Fine-Pitch Scaling Wall: Total Width Loss: Δw = 2 · δ_u ≈ 2 · d_seed · (R_lat / R_vert) • Isotropic Wet Etch Physics: Wet chemical etchants (H₂O₂/H₂SO₄ or persulfate) etch isotropically (R_lat ≈ R_vert). Removing 300 nm seed Cu removes ~600 nm total width from trace footprint. • Critical Yield Cliff at < 1.5 μm Line/Space: For a 1.0 μm trace, losing 0.6 μm reduces base width to 0.4 μm, triggering line lifting, collapse, and open circuits. • Foundry Transition to Dual-Damascene: Sub-micron RDL (< 1.0 μm) abandons SAP for oxide CMP.

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## 1. RDL Pitch Scaling Roadmap & Transmission Line Model

To satisfy the interconnect bandwidth density requirements of AI training processors and multi-die computing tiles, RDL scaling has progressed through three distinct architectural regimes.

RDL Interconnect Roadmap & High-Frequency Microstrip Model dimensional scaling from organic substrates to sub-micron damascene and transmission line impedance RDL DIMENSIONAL SCALING REGIMES 1. Standard Organic Build-Up (ABF) Line/Space: 10/10 to 15/15 μm | Vias: ~40 μm Wire density: ~50 lines/mm/layer | R_line: Low 2. Fine-Pitch Polymer SAP (InFO / FoCoS) Line/Space: 2/2 to 1.5/1.5 μm | Vias: ~3–5 μm Wire density: ~250–330 lines/mm/layer Dielectric: Photosensitive Polyimide (PSPI/PBO) 3. Sub-Micron Dual-Damascene (CoWoS-S) Line/Space: 0.4/0.4 to 0.8/0.8 μm | Vias: < 0.5 μm Wire density: > 1,000 lines/mm/layer Dielectric: PECVD SiO₂ / SiCN with Cu CMP Die-to-Die Interconnect Density: • Bandwidth Density: > 2.0–4.0 Tbps/mm per beach-front • Energy Per Bit: < 0.15–0.25 pJ/bit over 2–5 mm trace HIGH-FREQUENCY TRANSMISSION LINE MODEL RDL Ground Reference Plane (GND) Dielectric (h, ε_r) PSPI / PBO Signal (w, t) w t h Characteristic Impedance (Z₀ ≈ 50 Ω Target): Z₀ ≈ [87 / √(ε_r + 1.41)] · ln[ 5.98h / (0.8w + t) ] Skin Depth Attenuation (at > 10 GHz): δ_s = √( ρ / (π · f · μ) ) ≈ 0.66 μm at 10 GHz • At 28–56 GHz, current crowds into thin skin layer • Dielectric loss tangent: α_diel ∝ f · √ε_r · tan δ Material Parameter Comparison: • PSPI: ε_r ≈ 3.3, tan δ ≈ 0.008 | Cure Temp: 280°C–320°C • PBO: ε_r ≈ 2.9, tan δ ≈ 0.003 | Cure Temp: 200°C–220°C

### 1.1 Microstrip Impedance & Propagation Delay
For an RDL signal trace of width $w$ and thickness $t$ separated from a reference ground plane by a dielectric of thickness $h$ and relative permittivity $\epsilon_r$, the characteristic impedance $Z_0$ is governed by:

$$Z_0 \approx \frac{87}{\sqrt{\epsilon_r + 1.41}} \ln\left( \frac{5.98 h}{0.8 w + t} \right) \quad \text{for } \frac{w}{h} < 1.3$$

For fine-pitch RDL where $w/h \ge 1.3$, the Wheeler conformal mapping formulation applies:

$$Z_0 = \frac{120\pi}{\sqrt{\epsilon_{eff}} \left[ \frac{w}{h} + 1.393 + 0.667 \ln\left( \frac{w}{h} + 1.444 \right) \right]}$$

Where the effective permittivity $\epsilon_{eff}$ accounts for fringing electric field lines into the surrounding passivation:

$$\epsilon_{eff} \approx \frac{\epsilon_r + 1}{2} + \frac{\epsilon_r - 1}{2} \frac{1}{\sqrt{1 + 12 \frac{h}{w}}}$$

The signal propagation delay per unit length $\tau_{pd}$ is determined solely by the speed of light $c$ and the effective dielectric permittivity:

$$\tau_{pd} = \frac{\sqrt{\epsilon_{eff}}}{c} \approx 6.0\text{ to }6.8\,\text{ps/mm}$$

For a standard $5\,\text{mm}$ inter-chiplet bridge trace, the physical time-of-flight latency is approximately $30\text{ to }34\,\text{ps}$.

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## 2. Dielectric Material Selection: PSPI vs. PBO vs. Inorganic Thin Films

The dielectric matrix forms both the electrical isolation between metal routing planes and the mechanical buffer that absorbs thermal expansion mismatch.

+----------------------------------------------------------------------------------------------------+
|                                  RDL DIELECTRIC MATERIAL BENCHMARK                                 |
+--------------------+--------------------+--------------------+--------------------+----------------+
| MATERIAL           | DIELECTRIC CONST εr| LOSS TANGENT tan δ | CURE TEMPERATURE   | ELONGATION AT  |
|                    | (at 10 GHz)        | (at 10 GHz)        | (°C)               | BREAK (%)      |
+--------------------+--------------------+--------------------+--------------------+----------------+
| Photosensitive     | 3.2 to 3.4         | 0.007 to 0.010     | 280°C to 320°C     | 40% to 60%     |
| Polyimide (PSPI)   | (Moderate)         | (Standard loss)    | (High budget)      | (High ductil.) |
+--------------------+--------------------+--------------------+--------------------+----------------+
| Polybenzoxazole    | 2.8 to 2.9         | 0.003 to 0.004     | 200°C to 230°C     | 50% to 75%     |
| (PBO)              | (Low capacitance)  | (Low loss)         | (Low temp friendly)| (Superior)     |
+--------------------+--------------------+--------------------+--------------------+----------------+
| Benzocyclobutene   | 2.65               | 0.0008 to 0.0010   | 250°C              | 8% to 10%      |
| (BCB - Cyclotene)  | (Ultra-low k)      | (Extremely low)    | (Moderate)         | (Brittle)      |
+--------------------+--------------------+--------------------+--------------------+----------------+
| PECVD SiO₂ / SiCN  | 3.8 to 4.2         | 0.001 to 0.002     | 175°C to 250°C     | < 1%           |
| (Silicon Damascene)| (Inorganic / High) | (Low loss)         | (CVD budget)       | (Rigid ceramic)|
+--------------------+--------------------+--------------------+--------------------+----------------+

### 2.1 The Low-Temperature Cure Imperative
In Die-First FOWLP architectures, the active silicon dies are already embedded in an epoxy mold compound (EMC) before the RDL layers are deposited. Because organic mold compounds degrade and warp catastrophically when exposed to temperatures exceeding $230^\circ\text{C}\text{--}250^\circ\text{C}$, conventional high-temperature polyimides ($320^\circ\text{C}$ cure) cannot be utilized. Foundries utilize low-temperature cure PBO and modified polyimides that cross-link fully at $200^\circ\text{C}\text{--}220^\circ\text{C}$ while retaining high tensile elongation ($> 50\%$) to absorb shear warpage without micro-cracking.

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## 3. High-Frequency Attenuation: Skin Effect & Dielectric Loss

At millimeter-wave operating speeds ($> 10\text{ to }112\,\text{Gbps}$ PAM4), electromagnetic energy propagates within a shallow surface layer of the copper trace:

$$\delta_s = \sqrt{\frac{\rho_{Cu}}{\pi f \mu_0 \mu_r}}$$

Where:
- $\rho_{Cu} \approx 1.72 \times 10^{-8}\,\Omega\cdot\text{m}$ (resistivity of electroplated copper).
- $\mu_0 = 4\pi \times 10^{-7}\,\text{H/m}$ (vacuum magnetic permeability).
- $\mu_r \approx 1.0$ for non-magnetic copper.

At $f = 10\,\text{GHz}$, the skin depth is $\delta_s \approx 0.66\,\mu\text{m}$. At $f = 28\,\text{GHz}$, $\delta_s$ shrinks to $0.39\,\mu\text{m}$, which is smaller than the nominal physical thickness of the trace ($t = 2.0\,\mu\text{m}$). Consequently, the high-frequency conductor attenuation $\alpha_c$ increases with the square root of frequency:

$$\alpha_c(f) \approx \frac{R_{ac}(f)}{2 Z_0} = \frac{1}{2 Z_0} \left( \frac{\rho_{Cu}}{w \cdot \delta_s} \right) \propto \sqrt{f}$$

Simultaneously, the dielectric attenuation $\alpha_d$ scales linearly with frequency:

$$\alpha_d(f) = \frac{\pi f \sqrt{\epsilon_r}}{c} \cdot \tan\delta \propto f$$

At data rates exceeding $56\,\text{Gbps}$, dielectric loss dominates the channel insertion loss budget, mandating the transition from standard polyimides ($\tan\delta \approx 0.008$) to ultra-low-loss PBO or fluoropolymer dielectrics ($\tan\delta \le 0.003$).

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## 4. Failure Modes & Reliability Qualification

+----------------------------------------------------------------------------------------------------+
|                                    RDL RELIABILITY TEST MATRIX                                     |
+--------------------+--------------------+--------------------+-------------------------------------+
| FAILURE MECHANISM  | ROOT CAUSE         | STRESS TEST COND   | MITIGATION STRATEGY                 |
+--------------------+--------------------+--------------------+-------------------------------------+
| Interfacial        | Moisture uptake /  | Highly Accelerated | Surface silane adhesion promoters;  |
| Delamination       | poor polymer bond  | Stress Test (HAST) | Ar plasma pre-clean before seed PVD.|
+--------------------+--------------------+--------------------+-------------------------------------+
| Via Barrel         | CTE mismatch       | Thermal Shock      | Tapered via sidewall angle (65°-75°)|
| Cracking           | (Polymer vs. Cu)   | (-55°C to +125°C)  | prevents corner stress concentration|
+--------------------+--------------------+--------------------+-------------------------------------+
| Copper Migration / | Moisture + bias in | High Temperature   | Continuous Ta/Ti barrier encapsulation|
| Dendrite Shorting  | hydrophilic polymer| Operating Life     | prevents electrochemical migration. |
+--------------------+--------------------+--------------------+-------------------------------------+
| Trace Undercut     | Over-etching seed  | Visual Inspection  | Micro-crystalline thin Cu seed;     |
| Collapse           | layer in wet bath  | & Cross-Section SEM| switch to mSAP or dry plasma etch.  |
+--------------------+--------------------+--------------------+-------------------------------------+

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