fan out wafer level packaging

```svg Fan-out wafer-level packaging: no substrate, RDL straight on the dieDies re-molded into a wafer; copper RDL fans I/O out past the die edge — thinner and cheaper than a package substrate1 · The fan-out structurediemoldmoldRDL — Cu in polymerfan-outfan-outA die is re-molded into a wafer.Copper RDL is built on its face andfans I/O out past the die edge.No package substrate at all —RDL replaces it entirely.Package height can drop below0.5 mm — great for mobile SoCs.2 · Chip-first vs chip-lastChip-first (RDL last)1234Place dies on a carrierMold — reconstituted waferDebond the carrierBuild RDL on die face + ballsSimple RDL — but dies shift in the moldChip-last (RDL first)1234Build RDL on a carrier firstAttach known-good diesMold, then debondDrop balls + singulateRDL proven first — less die-shiftBoth skip the substrate; order tradesyield against process steps.3 · Why it wins & hard partsWhy it winsNo substrate → package < 0.5 mmCheaper — ~50–70% vs substrateShort RDL → better electricalDie near board → better thermalScales: InFO-PoP, InFO-LThe hard partsdie-shift & placement accuracyreconstituted-wafer warpageRDL yield over a large areathermal for high-power devicesWarpage and die movement in themold are the yield gate.No substrate, RDL on the dieCopper redistribution is built straightonto the molded die face; the organicpackage substrate disappears.Fan-out adds I/O roomRouting past the die edge gives moreballs at board-friendly pitch thanfan-in WLCSP can.Warpage & die-shift biteReconstituted-wafer warpage and diemovement in the mold gate FOWLPyield. ``` **Fan-Out Wafer-Level Packaging (FOWLP)** is the **advanced high-density packaging technology that eliminates the bulky traditional organic substrate entirely, instead embedding bare silicon dies directly into a reconstituted wafer made of epoxy mold compound, then routing ultra-thin copper redistributions layers (RDLs) "fanning out" from the die to the solder balls**. Before FOWLP, mobile processors were placed on a fiberglass-like organic substrate (a tiny green PCB), wire-bonded or flip-chipped to it, and then the substrate routed the signals to the larger solder balls on the bottom (BGA). This substrate added immense thickness, electrical resistance, and cost to smartphones. **The Fan-Out Revolution**: FOWLP completely changed mobile packaging (famously debuting as TSMC's "InFO" for the Apple A10 processor). 1. **Reconstituted Wafer**: Instead of substrates, thousands of known good dies (KGD) are picked and placed face-down on a temporary glass carrier with high precision. 2. **Overmolding**: A thick layer of liquid epoxy mold compound is poured over the dies, encapsulating them. Once cured, the glass carrier is stripped away, leaving a solid, artificial "reconstituted wafer" of epoxy with the active silicon faces perfectly flush with the surface. 3. **RDL and "Fanning Out"**: Lithography tools (similar to those used in the fab) directly pattern incredibly dense, microscopic copper wires (Redistribution Layers, RDL) across the surface of the epoxy. Because the epoxy package is larger than the silicon die itself, these wires "fan out" to a wider area, creating room for hundreds of standard solder balls to connect to the motherboard. **The Advantages**: - **Unprecedented Thinness**: By eliminating the substrate, chips became incredibly thin (e.g., <0.5mm), making ultra-thin smartphones possible. - **Electrical Performance**: Shorter interconnects and fewer transition materials drastically lower parasitic inductance and capacitance, allowing for higher speed signal transfer (especially to mobile LPDDR RAM mounted directly on top of the FOWLP using Package-on-Package techniques). - **Multi-Die Integration**: Modern multi-die FOWLP allows heterogeneous integration of logic, memory, and high-frequency RF chips side-by-side in a single molded package with routing densities unachievable on standard substrates.

Go deeper with CFSGPT

Get AI-powered deep-dives, save terms, and run advanced simulations — free account.

Create Free Account