fan out wafer level fowlp

```svg Fan-out wafer-level packaging: no substrate, RDL straight on the dieDies re-molded into a wafer; copper RDL fans I/O out past the die edge — thinner and cheaper than a package substrate1 · The fan-out structurediemoldmoldRDL — Cu in polymerfan-outfan-outA die is re-molded into a wafer.Copper RDL is built on its face andfans I/O out past the die edge.No package substrate at all —RDL replaces it entirely.Package height can drop below0.5 mm — great for mobile SoCs.2 · Chip-first vs chip-lastChip-first (RDL last)1234Place dies on a carrierMold — reconstituted waferDebond the carrierBuild RDL on die face + ballsSimple RDL — but dies shift in the moldChip-last (RDL first)1234Build RDL on a carrier firstAttach known-good diesMold, then debondDrop balls + singulateRDL proven first — less die-shiftBoth skip the substrate; order tradesyield against process steps.3 · Why it wins & hard partsWhy it winsNo substrate → package < 0.5 mmCheaper — ~50–70% vs substrateShort RDL → better electricalDie near board → better thermalScales: InFO-PoP, InFO-LThe hard partsdie-shift & placement accuracyreconstituted-wafer warpageRDL yield over a large areathermal for high-power devicesWarpage and die movement in themold are the yield gate.No substrate, RDL on the dieCopper redistribution is built straightonto the molded die face; the organicpackage substrate disappears.Fan-out adds I/O roomRouting past the die edge gives moreballs at board-friendly pitch thanfan-in WLCSP can.Warpage & die-shift biteReconstituted-wafer warpage and diemovement in the mold gate FOWLPyield. ``` **Fan-Out Wafer-Level Packaging (FOWLP)** is **substrate-less advanced packaging distributing dies within a mold compound, building RDL layers for fine-pitch interconnect and multi-die integration**. **Reconstituted Wafer Process:** - Create artificial wafer: singulated dice → embed in mold compound → new wafer - Mold compound: epoxy matrix, filled with silica for CTE control - Wafer formation: grind top flat, polish → pseudo-wafer ready for RDL processing - Advantage: heterogeneous die support (different sizes, technologies) - Cost: multiple material steps (embedding, grinding, polishing) **Chip-First vs Chip-Last Sequence:** - Chip-first: bond dies to carrier → embed mold → RDL on top - Chip-last: build RDL first on reconstituted wafer → attach dies retroactively - Chip-first advantage: simpler RDL design (known die locations) - Chip-last advantage: no pressure damage risk during embedding **RDL (Redistribution Layer) Routing:** - Fine-pitch implementation: 5-10 µm lines/spaces achievable - Multi-layer RDL: 3-5 metal layers typical for complex routing - Via formation: laser or photolithography for inter-layer connections - Material: sputtered seed + electroplated copper - Dielectric: polymer (polyimide, PBO) with low Dk ~3 **Commercial FOWLP Variants:** - TSMC InFO: integrated fan-out (embedded module process) - ASE FOCoS: fan-out chip-size - Intel EMIB: embedded multi-die interconnect bridge (hybrid bonding alternative) - Amkor UTMOS: universal test module on substrate **Warpage and Reliability Challenges:** - Warpage: mold compound CTE mismatch with silicon creates stress - Moisture absorption: organic dielectric absorbs humidity, swelling induces stress - Reflow cycles: thermal mismatch causes solder fatigue - Underfill: common practice to mitigate mechanical stress **Multi-Die Integration:** - Chiplet assembly: heterogeneous dies (different process nodes) in single package - Mixed high-performance + low-power: e.g., GPU + HBM DRAM + power management - Signal routing complexity: RDL length/loss minimization - Power distribution: decoupling capacitors on substrate or embedded **FOWLP Advantages vs Traditional Packaging:** - No substrate expense: reduced material cost - Short interconnect: lower parasitic inductance/capacitance - Heterogeneous integration: mix process technologies - Density: higher than BGA, approaching chiplet-on-chiplet stacking **Yield and Manufacturing:** - Embedding yield: handling/cracking during compaction - RDL yield: line/space defects in fine-pitch routing - Known good die (KGD) testing: critical before embedding - Repair difficulty: limited ECO (engineering change order) post-embedding FOWLP enables competitive cost/performance for heterogeneous systems while avoiding organic substrate and enabling finer pitch than traditional BGA packaging.

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