fan out wafer level fowlp

**Fan-Out Wafer-Level Packaging (FOWLP)** is **substrate-less advanced packaging distributing dies within a mold compound, building RDL layers for fine-pitch interconnect and multi-die integration**. **Reconstituted Wafer Process:** - Create artificial wafer: singulated dice → embed in mold compound → new wafer - Mold compound: epoxy matrix, filled with silica for CTE control - Wafer formation: grind top flat, polish → pseudo-wafer ready for RDL processing - Advantage: heterogeneous die support (different sizes, technologies) - Cost: multiple material steps (embedding, grinding, polishing) **Chip-First vs Chip-Last Sequence:** - Chip-first: bond dies to carrier → embed mold → RDL on top - Chip-last: build RDL first on reconstituted wafer → attach dies retroactively - Chip-first advantage: simpler RDL design (known die locations) - Chip-last advantage: no pressure damage risk during embedding **RDL (Redistribution Layer) Routing:** - Fine-pitch implementation: 5-10 µm lines/spaces achievable - Multi-layer RDL: 3-5 metal layers typical for complex routing - Via formation: laser or photolithography for inter-layer connections - Material: sputtered seed + electroplated copper - Dielectric: polymer (polyimide, PBO) with low Dk ~3 **Commercial FOWLP Variants:** - TSMC InFO: integrated fan-out (embedded module process) - ASE FOCoS: fan-out chip-size - Intel EMIB: embedded multi-die interconnect bridge (hybrid bonding alternative) - Amkor UTMOS: universal test module on substrate **Warpage and Reliability Challenges:** - Warpage: mold compound CTE mismatch with silicon creates stress - Moisture absorption: organic dielectric absorbs humidity, swelling induces stress - Reflow cycles: thermal mismatch causes solder fatigue - Underfill: common practice to mitigate mechanical stress **Multi-Die Integration:** - Chiplet assembly: heterogeneous dies (different process nodes) in single package - Mixed high-performance + low-power: e.g., GPU + HBM DRAM + power management - Signal routing complexity: RDL length/loss minimization - Power distribution: decoupling capacitors on substrate or embedded **FOWLP Advantages vs Traditional Packaging:** - No substrate expense: reduced material cost - Short interconnect: lower parasitic inductance/capacitance - Heterogeneous integration: mix process technologies - Density: higher than BGA, approaching chiplet-on-chiplet stacking **Yield and Manufacturing:** - Embedding yield: handling/cracking during compaction - RDL yield: line/space defects in fine-pitch routing - Known good die (KGD) testing: critical before embedding - Repair difficulty: limited ECO (engineering change order) post-embedding FOWLP enables competitive cost/performance for heterogeneous systems while avoiding organic substrate and enabling finer pitch than traditional BGA packaging.