Fan Out Wafer Level Packaging

# Fan-Out Wafer-Level Packaging (FOWLP): Architectures, Die Shift & Panel Mechanics

In modern heterogeneous computing and high-density chiplet integration, Fan-Out Wafer-Level Packaging (FOWLP) and Fan-Out Panel-Level Packaging (FOPLP) (exemplified by commercial platforms such as TSMC InFO, Infineon eWLB, ASE FoCoS, and Samsung FOPLP) provide a substrate-less packaging architecture that eliminates conventional organic flip-chip ball grid array (BGA) package substrates.

By dicing singularized Known Good Dies (KGD) from tested silicon wafers and embedding them within an Epoxy Mold Compound (EMC) matrix, manufacturers create an artificial, reconstituted wafer ($300\,\text{mm}$) or large-format rectangular panel ($510 \times 515\,\text{mm}$). High-density thin-film redistribution layers (RDL) are then fabricated across both the active die surface and the surrounding mold compound. This structural "fan-out" expands the routing footprint beyond the original silicon boundary, slashing package vertical height by $> 50\%$, minimizing parasitic interconnect inductance ($L_{interconnect} < 0.1\text{ to }0.3\,\text{nH}$), and enabling high-bandwidth multi-die inter-chiplet routing.

FOWLP Architectures: Die-First vs. Die-Last (RDL-First) process flow comparison, reconstituted mold matrix, and interconnect layer sequencing 1. DIE-FIRST FACE-DOWN FLOW Temporary Carrier + Thermal Release Tape Known Good Die (KGD) Active Face Down (Die Pads Contact Tape) EMC EMC Exposed Reconstituted Surface Redistribution Layers (Fan-Out Area) Characteristics & Trade-offs: • Lowest process cost and shortest thermal path • Excellent heat dissipation from exposed silicon back • Vulnerable to Die Shift during mold injection/cure • RDL yield loss discards already-embedded known dies • Standard for smartphone application processors (AP) and power management ICs (PMICs). 2. DIE-LAST (RDL-FIRST) FLOW Glass / Silicon Carrier Wafer Fine-Pitch Multi-Layer RDL (1.5/1.5 μm) Logic Die HBM / Chiplet EMC UV Laser Release of Glass Carrier Characteristics & Trade-offs: • Zero Die Shift during RDL: RDL built on pristine carrier • Highest density routing: achieves sub-2 μm L/S • Defective RDL rejected before expensive dies attached • Ideal for multi-chiplet AI processors and CoWoS-R • Requires high-accuracy flip-chip bonding and underfill prior to mold encapsulation.

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## 1. Die Shift Mechanics & Adaptive Patterning Lithography

In Die-First FOWLP and FOPLP manufacturing flows, singularized silicon dies are placed face-down on a carrier tape using high-speed pick-and-place tools. During transfer or compression molding, the molten epoxy mold compound (EMC) is injected under high pressure ($3\text{ to }7\,\text{MPa}$) at elevated temperatures ($125^\circ\text{C}\text{ to }165^\circ\text{C}$).

Die Shift Mechanics & Adaptive Patterning Lithography fluid-induced die displacement, optical coordinate mapping, and dynamic stepper shot correction DIE SHIFT & VIA OVERLAY FAILURE Nominal Design Position Shifted Die (Δx, Δy, Δθ Shift) Pad Shift Vector Fixed Mask Via (OVERLAY MISALIGNMENT) Root Causes of Die Shift: 1. Viscous drag of mold compound during resin front propagation 2. Volumetric chemical shrinkage of epoxy resin during cure (0.1–0.3%) 3. CTE mismatch thermal contraction between mold and silicon Typical Displacement: Δx, Δy = 5–20 μm, Δθ = 0.1°–0.5° ADAPTIVE PATTERNING (AP) SOLUTION 1. High-Speed Optical Inspection (AOI): High-resolution camera scans entire 300 mm wafer / panel. Extracts exact (x, y, θ) center of every die pad. 2. Real-Time Adaptive CAD Computation: Software recalculates RDL via locations & routing vectors. Morphs interconnect traces to match true die coordinates. 3. Maskless Laser Direct Imaging (LDI): Direct-write digital lithography exposes photoresist dynamically. Via lands perfectly centered on shifted pads: Yield > 99.8% Mathematical Coordinate Mapping: r_actual = R(θ_shift) · r_nominal + [ Δx_shift , Δy_shift ]^T • Overcoming Fixed Reticle Limitations: Fixed optical reticles cannot adapt to non-uniform die shift, limiting standard steppers to relaxed via pitches (> 15 μm). • Sub-2 μm L/S Scaling: Adaptive patterning enables sub-2 μm RDL scaling on large reconstituted wafers without die-shift yield loss.

### 1.1 Mathematical Formulation of Die Shift
The actual position of a contact pad $\vec{r}_{pad,actual}$ following mold cure is governed by a 2D affine transformation comprising translation ($\Delta x, \Delta y$) and rigid-body rotation ($\Delta \theta$):

$$\begin{pmatrix} x_{pad,actual} \\ y_{pad,actual} \end{pmatrix} = \begin{pmatrix} \cos\Delta\theta & -\sin\Delta\theta \\ \sin\Delta\theta & \cos\Delta\theta \end{pmatrix} \begin{pmatrix} x_{nominal} \\ y_{nominal} \end{pmatrix} + \begin{pmatrix} \Delta x_{shift} \\ \Delta y_{shift} \end{pmatrix}$$

For conventional fixed-photomask projection steppers, the alignment error margin $E_{overlay}$ must encompass both lithographic stage accuracy $\epsilon_{stage}$ and the maximum die displacement envelope:

$$E_{overlay} = \sqrt{\epsilon_{stage}^2 + \Delta x_{max}^2 + \Delta y_{max}^2} + r_{pad} \cdot \sin(\Delta\theta_{max})$$

When $\Delta x_{max} \approx 10\,\mu\text{m}$, fixed-mask lithography requires capture pads with diameter $D_{pad} \ge 25\text{ to }30\,\mu\text{m}$, severely restricting interconnect routing density. Adaptive Patterning (AP) replaces physical masks with digital spatial light modulators or laser direct imaging (LDI), dynamically offsetting the exposure path for each die so that:

$$\vec{r}_{via,exposure} = \vec{r}_{pad,actual} \pm \epsilon_{LDI} \quad (\epsilon_{LDI} \le 0.5\,\mu\text{m})$$

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## 2. Viscoelastic Mold Cure Kinetics & Panel Warpage

Epoxy Mold Compounds (EMC) consist of biphenyl or epoxy cresol novolac resins filled with $80\text{ to }90\,\text{wt}\%$ fused spherical silica ($\text{SiO}_2$) nanoparticles to lower the effective coefficient of thermal expansion ($\alpha_{EMC} \approx 7\text{ to }12\,\text{ppm/K}$).

+----------------------------------------------------------------------------------------------------+
|                                    EPOXY MOLD COMPOUND (EMC) PROPERTIES                            |
+--------------------+--------------------+--------------------+--------------------+----------------+
| PARAMETER          | BELOW Tg (< 140°C) | ABOVE Tg (> 140°C) | SILICON REFERENCE  | IMPACT ON FLOW |
+--------------------+--------------------+--------------------+--------------------+----------------+
| Young's Modulus E  | 18 to 26 GPa       | 0.8 to 1.5 GPa     | 130 to 169 GPa     | Elastic modulus|
|                    | (Glassy state)     | (Rubbery state)    | (Elastic crystal)  | drops 20x > Tg |
+--------------------+--------------------+--------------------+--------------------+----------------+
| CTE (α)            | 7 to 10 ppm/K      | 25 to 38 ppm/K     | 2.6 ppm/K          | CTE increases  |
|                    | (Alpha-1)          | (Alpha-2)          | (Constant)         | 3x-4x above Tg |
+--------------------+--------------------+--------------------+--------------------+----------------+
| Chemical Cure      | —                  | 0.15% to 0.25%     | 0.0%               | Cross-linking  |
| Shrinkage (ΔV/V)   | (Locked-in strain) | (Active reaction)  | (Zero)             | contracts resin|
+--------------------+--------------------+--------------------+--------------------+----------------+

### 2.1 The Two-Component Residual Stress Formulation
The total thermo-mechanical stress $\sigma_{residual}$ locked into a reconstituted wafer upon cooling from mold cure temperature ($T_{cure} \approx 150^\circ\text{C}\text{ to }175^\circ\text{C}$) to room temperature ($T_{room} = 25^\circ\text{C}$) is the sum of chemical polymerization shrinkage and thermal expansion mismatch:

$$\sigma_{residual} = \underbrace{\frac{E_{EMC}}{3(1 - \nu_{EMC})} \left( \frac{\Delta V}{V_0} \right)}_{\text{Chemical Shrinkage Stress}} + \underbrace{\int_{T_{room}}^{T_{cure}} \frac{E_{EMC}(T)}{1 - \nu_{EMC}(T)} \left[ \alpha_{EMC}(T) - \alpha_{Si} \right] \, dT}_{\text{Thermal Expansion Mismatch Stress}}$$

Because $\alpha_{EMC} > \alpha_{Si}$, the mold compound contracts more aggressively than the embedded silicon dies during cooling, inducing severe concave (cryogenic "bowl") warpage.

### 2.2 Rectangular Panel Warpage Scaling: Wafer vs. Panel
In Fan-Out Panel-Level Packaging (FOPLP), processing transitions from circular $300\,\text{mm}$ wafers to large rectangular panels ($510 \times 515\,\text{mm}$ or $600 \times 600\,\text{mm}$) to achieve $> 3\times$ area scaling and lower unit cost.

However, out-of-plane warpage $\Delta \text{Bow}$ scales with the square of the panel diagonal $L_{panel}$:

$$\Delta \text{Bow} \propto \frac{L_{panel}^2}{h_{total}^2} \cdot \Delta \alpha \cdot \Delta T$$

Comparing a $300\,\text{mm}$ wafer ($L_{diag} = 300\,\text{mm}$) to a $510 \times 515\,\text{mm}$ panel ($L_{diag} \approx 725\,\text{mm}$):

$$\text{Warpage Multiplier} = \left( \frac{725\,\text{mm}}{300\,\text{mm}} \right)^2 \approx 5.84\times$$

Uncompensated $510 \times 515\,\text{mm}$ panels can exhibit out-of-plane warpage exceeding $5\text{ to }12\,\text{mm}$, preventing vacuum chuck sealing and causing catastrophic optical defocus. Foundries eliminate this deformation by depositing a matched Backside Warpage Balance Layer (a counteracting polymer or inorganic dielectric layer on the rear panel face) to equalize bending moments.

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## 3. High-Density Multi-Die Heterogeneous Integration (e.g., TSMC InFO-L / InFO-SoIS)

Advanced mobile application processors and high-performance computing (HPC) chiplets integrate logic SoCs alongside High-Bandwidth Memory (HBM) and power delivery dies within a unified fan-out package:

+----------------------------------------------------------------------------------------------------+
|                                    ADVANCED FAN-OUT INTEGRATION VARIANTS                           |
+--------------------+--------------------+--------------------+-------------------------------------+
| PLATFORM           | CORE STRUCTURE     | MINIMUM PITCH      | APPLICATION TARGET                  |
+--------------------+--------------------+--------------------+-------------------------------------+
| InFO-PoP           | Through-InFO Vias  | 1.5 / 1.5 μm L/S   | Mobile Flagship APs (Apple A-series)|
| (Package-on-Pack.) | (TIV) to top DRAM  | 130 μm TIV pitch   | Lowest profile smartphone processor |
+--------------------+--------------------+--------------------+-------------------------------------+
| InFO-L / InFO-oS   | Embedded Local Si  | 0.8 / 0.8 μm RDL   | High-Performance Computing / AI     |
| (Interconnect Sub.)| Bridge (LSI) die   | sub-micron bridge  | Multi-chiplet heterogeneous compute |
+--------------------+--------------------+--------------------+-------------------------------------+
| FoCoS              | Fan-Out Chip on    | 2.0 / 2.0 μm RDL   | Server Switches & Networking ASICs  |
| (ASE Chip-on-Sub.) | Substrate with BGA | 40 μm micro-bumps  | Replaces expensive Si interposers   |
+--------------------+--------------------+--------------------+-------------------------------------+

### 3.1 Through-InFO Vias (TIV) for 3D Package-on-Package (PoP)
In mobile PoP assemblies, the application processor is packaged in the lower FOWLP module, while an LPDDR5X DRAM package is stacked directly on top. Vertical electrical connectivity is established through Through-InFO Vias (TIV): tall electrolytic copper pillars ($h \approx 150\text{ to }220\,\mu\text{m}$, diameter $d \approx 80\text{ to }100\,\mu\text{m}$) electroplated prior to mold encapsulation. TIVs provide superior high-frequency signal integrity compared to conventional wire-bonded PoP substrates, reducing DRAM power consumption by $> 20\%$ and boosting interface bandwidth to over $8.5\,\text{Gbps}$ per pin.

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