info (integrated fan-out)

Integrated Fan-Out is TSMC's **fan-out wafer-level packaging technology** that redistributes die I/O to a larger area **without a traditional package substrate**. First used in Apple's **A10 processor** (iPhone 7, 2016). **Why Fan-Out?** **No substrate**: Eliminates the organic package substrate, reducing package height and cost. **Shorter interconnects**: RDL traces are shorter than substrate routing, improving electrical performance. **Thinner package**: Total package height **< 0.5mm** possible. Critical for mobile devices. **Better thermal**: Die is closer to the board, improving heat dissipation. **InFO Process Flow** **Step 1 - Die Placement**: Known-good dies placed face-down on temporary carrier with precise spacing. **Step 2 - Molding**: Epoxy mold compound (EMC) encapsulates dies, creating a reconstituted wafer. **Step 3 - Carrier Removal**: Temporary carrier debonded, exposing die pads. **Step 4 - RDL Formation**: Redistribution layers (Cu traces in polymer dielectric) fabricated on the die surface to fan out connections. **Step 5 - Ball Drop**: Solder balls placed on RDL pads at board-level pitch. **Step 6 - Singulation**: Reconstituted wafer diced into individual packages. **InFO Variants** • **InFO-PoP (Package on Package)**: Memory package stacked on top. Used in smartphone processors. • **InFO-L (Large)**: Extended fan-out for larger dies or multi-die integration. • **InFO-SoW (System on Wafer)**: Multiple chiplets integrated in a single InFO package for HPC applications. • **InFO-3D**: Combines fan-out with 3D die stacking for maximum integration density.