info (integrated fan-out)

```svg Fan-out wafer-level packaging: no substrate, RDL straight on the dieDies re-molded into a wafer; copper RDL fans I/O out past the die edge — thinner and cheaper than a package substrate1 · The fan-out structurediemoldmoldRDL — Cu in polymerfan-outfan-outA die is re-molded into a wafer.Copper RDL is built on its face andfans I/O out past the die edge.No package substrate at all —RDL replaces it entirely.Package height can drop below0.5 mm — great for mobile SoCs.2 · Chip-first vs chip-lastChip-first (RDL last)1234Place dies on a carrierMold — reconstituted waferDebond the carrierBuild RDL on die face + ballsSimple RDL — but dies shift in the moldChip-last (RDL first)1234Build RDL on a carrier firstAttach known-good diesMold, then debondDrop balls + singulateRDL proven first — less die-shiftBoth skip the substrate; order tradesyield against process steps.3 · Why it wins & hard partsWhy it winsNo substrate → package < 0.5 mmCheaper — ~50–70% vs substrateShort RDL → better electricalDie near board → better thermalScales: InFO-PoP, InFO-LThe hard partsdie-shift & placement accuracyreconstituted-wafer warpageRDL yield over a large areathermal for high-power devicesWarpage and die movement in themold are the yield gate.No substrate, RDL on the dieCopper redistribution is built straightonto the molded die face; the organicpackage substrate disappears.Fan-out adds I/O roomRouting past the die edge gives moreballs at board-friendly pitch thanfan-in WLCSP can.Warpage & die-shift biteReconstituted-wafer warpage and diemovement in the mold gate FOWLPyield. ``` Integrated Fan-Out is TSMC's **fan-out wafer-level packaging technology** that redistributes die I/O to a larger area **without a traditional package substrate**. First used in Apple's **A10 processor** (iPhone 7, 2016). **Why Fan-Out?** **No substrate**: Eliminates the organic package substrate, reducing package height and cost. **Shorter interconnects**: RDL traces are shorter than substrate routing, improving electrical performance. **Thinner package**: Total package height **< 0.5mm** possible. Critical for mobile devices. **Better thermal**: Die is closer to the board, improving heat dissipation. **InFO Process Flow** **Step 1 - Die Placement**: Known-good dies placed face-down on temporary carrier with precise spacing. **Step 2 - Molding**: Epoxy mold compound (EMC) encapsulates dies, creating a reconstituted wafer. **Step 3 - Carrier Removal**: Temporary carrier debonded, exposing die pads. **Step 4 - RDL Formation**: Redistribution layers (Cu traces in polymer dielectric) fabricated on the die surface to fan out connections. **Step 5 - Ball Drop**: Solder balls placed on RDL pads at board-level pitch. **Step 6 - Singulation**: Reconstituted wafer diced into individual packages. **InFO Variants** • **InFO-PoP (Package on Package)**: Memory package stacked on top. Used in smartphone processors. • **InFO-L (Large)**: Extended fan-out for larger dies or multi-die integration. • **InFO-SoW (System on Wafer)**: Multiple chiplets integrated in a single InFO package for HPC applications. • **InFO-3D**: Combines fan-out with 3D die stacking for maximum integration density.

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