semiconductor advanced packaging fan out

**Fan-Out Wafer-Level Packaging (FOWLP)** is the **advanced packaging technology that creates a larger effective die area by reconstructing dies on a carrier wafer with additional space around each die for redistributing I/O connections outward — enabling more I/O pins than the die perimeter allows, thinner packages than traditional BGA or flip-chip, and direct integration of passive components, making it the platform for smartphone application processors (TSMC InFO) and increasingly for high-performance computing chiplet integration**. **Why Fan-Out** Traditional packaging: die pads are at the perimeter. I/O count is limited by perimeter × minimum pad pitch. For small dies (<5mm) this severely limits I/O count. Fan-out solves this by extending the routing area beyond the die edge, "fanning out" connections to a larger ball grid on the package surface. **Fan-Out Process Flow** 1. **Die Placement**: Known-good dies are picked from their original wafer and placed face-down onto a temporary carrier with precise positioning (±1-2 μm accuracy). Dies can come from different wafers, different processes, or even different foundries. 2. **Molding (Reconstitution)**: Epoxy mold compound is applied over and around the dies, encapsulating them in a reconstituted wafer (typically 300mm or 330mm). After curing and carrier removal, a flat surface with exposed die pads is obtained. 3. **RDL (Redistribution Layer) Formation**: Thin-film metal layers (Cu) with dielectric insulation (polyimide or PBO) are built on the exposed surface using lithography and plating — creating the fan-out routing that connects die pads to the larger-pitch solder ball locations. Modern FOWLP uses 2-5 RDL layers with 2-5 μm line/space. 4. **Ball Attach**: Solder balls are placed on the outermost RDL pads. 5. **Singulation**: The reconstituted wafer is diced into individual packages. **TSMC InFO (Integrated Fan-Out)** TSMC's InFO is the highest-volume fan-out packaging technology, used for Apple A-series and M-series processors since 2016. InFO advantages over traditional flip-chip: - **Thinner**: No substrate required (RDL replaces package substrate). Total package height reduction of 20-30%. - **Better Electrical**: Shorter interconnect paths (lower inductance, lower resistance). Improved power delivery. - **Better Thermal**: Die backside exposed for direct heat sink attachment. **Variants** - **InFO-PoP (Package on Package)**: DRAM package stacked on top of the InFO logic package. Used in Apple iPhone processors. - **InFO-oS (on Substrate)**: Fan-out package mounted on an organic substrate for larger die/multi-die integration. - **eWLB (Infineon/STATS ChipPAC)**: An early commercial FOWLP platform using a simpler reconstitution approach. Used for RF front-end modules and MEMS. - **Fan-Out Panel-Level Packaging (FOPLP)**: Uses large rectangular panels (510×515mm²) instead of round wafers for reconstitution. ~3x more packages per panel than per wafer. Lower cost per unit area but faces challenges in die placement accuracy and RDL lithography on large panels. Fan-Out Wafer-Level Packaging is **the packaging technology that freed I/O count from die size** — reconstructing semiconductor dies in a larger mold compound canvas that provides the routing real estate for hundreds of connections, enabling tiny dies to connect to the world with the I/O density previously reserved for much larger packages.