ion implantation cmos
**Ion Implantation and Dopant Activation** is the **precision doping technique that bombards the semiconductor surface with accelerated dopant ions (B, P, As, In) at controlled energy (0.2-500 keV) and dose (10¹¹-10¹⁶ cm⁻²) to create the junction profiles, threshold voltage adjustments, and contact doping that define transistor electrical behavior — followed by thermal activation anneals that repair implant damage and place dopant atoms onto electrically active substitutional lattice sites**.
**Ion Implantation Process**
1. **Ion Source**: Dopant-containing gas (BF₃, PH₃, AsH₃) is ionized in a plasma source. The desired ion species is selected by a mass-analyzing magnet (±1 amu resolution).
2. **Acceleration**: Ions are accelerated through an electrostatic potential (200 eV to 500 keV). Energy determines implant depth: 1-10 keV for shallow junctions (<20nm), 100-500 keV for deep wells.
3. **Beam Scanning**: The ion beam is electrostatically or mechanically scanned across the wafer to achieve uniform dose. Dose uniformity <0.5% (1σ) across 300mm wafers.
4. **Dose Control**: Beam current is measured by a Faraday cup. Total dose is the integral of current × time / (charge × area). Real-time dose uniformity monitoring ensures specification compliance.
**Channeling and Amorphization**
- **Channeling**: When the ion beam aligns with a crystal axis, ions travel deep between lattice planes with minimal scattering, creating an unwanted deep dopant tail. Prevention: tilt the wafer 7° and rotate 22° from the major crystal axis; use pre-amorphization implant (PAI) with Ge or Si ions to destroy the crystal structure before dopant implant.
- **Amorphization**: At sufficient dose (>10¹⁴ cm⁻² for heavy ions), accumulated collision damage converts crystalline silicon to amorphous. The amorphous layer must be re-crystallized by annealing — solid phase epitaxial regrowth (SPER) proceeds from the crystalline/amorphous interface at 500-600°C.
**Activation Anneal Technologies**
| Technique | Temperature | Time | Application |
|-----------|-------------|------|-------------|
| RTA (Rapid Thermal Anneal) | 950-1100°C | 1-10 seconds | Standard activation |
| Spike Anneal | 1000-1100°C | ~1 ms at peak | Minimize diffusion |
| Millisecond Anneal (Flash/Laser) | 1100-1350°C | 0.1-3 ms | Ultra-shallow junctions |
| Microwave Anneal | 400-600°C | Minutes | Low thermal budget (3D integration) |
**The Activation-Diffusion Tradeoff**
Higher anneal temperature activates more dopants (places them on substitutional sites) but also causes diffusion (dopants move, broadening the junction). For sub-10nm junction depths, millisecond anneals achieve >90% activation with <1nm diffusion by heating only the wafer surface for microseconds — thermal diffusion length scales as √(D×t), so reducing t from seconds to milliseconds reduces diffusion by 1000x.
**Advanced Doping for FinFET/Nanosheet**
- **Plasma Doping (PLAD)**: Immerses the wafer in a dopant plasma and applies a bias to accelerate ions conformally onto 3D surfaces. Better angular coverage of fin sidewalls than beam-line implant.
- **Molecular Beam Doping**: Ultra-low-energy (<1 keV) implant using molecular ions (B₁₈H₂₂⁺) that deliver high dose at extremely shallow depth without substrate amorphization.
Ion Implantation is **the surgical precision tool of semiconductor doping** — placing exactly the right number of dopant atoms at exactly the right depth with sub-nanometer control, enabling the junction engineering that determines every transistor's threshold voltage, leakage current, and switching speed.