ion implantation semiconductor

**Ion Implantation** is the **CMOS doping technique that introduces precisely controlled quantities of dopant atoms (boron, phosphorus, arsenic, indium) into the silicon substrate by accelerating ionized atoms to specific energies (0.2-3000 keV) and directing them at the wafer — achieving doping concentration control within ±1-2%, depth profile accuracy within ±5%, and spatial precision defined by the masking layers, making it the universal method for forming wells, channel doping, source/drain junctions, and threshold voltage adjustment in every CMOS process**. **How Ion Implantation Works** 1. **Ion Source**: Gaseous precursors (BF₃ for boron, PH₃ for phosphorus, AsH₃ for arsenic) are ionized in a plasma arc chamber. Mass spectrometry selects the desired ion species (e.g., ¹¹B⁺ from BF₃). 2. **Acceleration**: The selected ions are accelerated through an electric potential (0.2 keV to 3 MeV). Energy determines depth: higher energy → deeper implant. Typical ranges: 5-50 keV for shallow S/D extensions, 100-500 keV for deep wells. 3. **Beam Scanning**: The ion beam is electrostatically or mechanically scanned across the wafer to achieve uniform dose. The wafer is typically tilted (7°) and rotated to minimize channeling. 4. **Dose Control**: The total number of implanted ions per cm² (dose) is controlled by measuring beam current × exposure time. Typical doses range from 10¹¹ cm⁻² (threshold adjust) to 10¹⁶ cm⁻² (heavy S/D doping). **Channeling** If ions enter the silicon crystal along a major crystallographic axis (e.g., <110>), they can travel deep into the lattice between atom rows (channels) with minimal scattering — creating a much deeper dopant profile than intended. Channeling is prevented by tilting the wafer 7° off-axis and/or pre-amorphizing the surface with a Ge or Si implant that destroys the crystal order. **Implant Damage and Annealing** Each implanted ion displaces ~1000 silicon atoms from their lattice sites, creating point defects (vacancies, interstitials) and amorphous zones. The crystalline damage must be repaired and the dopant atoms must be placed on substitutional lattice sites (electrically activated) by thermal annealing: - **Rapid Thermal Anneal (RTA)**: 950-1100°C for 1-10 seconds. Standard for junction activation. - **Spike Anneal**: 1000-1100°C for <1 second. Minimizes dopant diffusion while maximizing activation. - **Laser Anneal (LSA)**: Millisecond-scale heating of only the surface layer to >1300°C. Achieves near-100% activation with negligible diffusion. Critical for ultra-shallow junctions at advanced nodes. **Advanced Implant Techniques** - **Plasma Doping (PLAD/PIII)**: Instead of a focused beam, the wafer is immersed in a plasma of dopant ions and biased with a pulsed negative voltage. Ions are extracted from the plasma and implanted uniformly across the surface. High dose rate for conformal doping of 3D structures (FinFET fins). - **Cluster Ion Implant**: Implanting molecular clusters (B₁₈H₂₂⁺) delivers multiple dopant atoms per implant event at very low energy per atom, enabling ultra-shallow doping without the beam extraction challenges of low-energy monatomic implants. Ion Implantation is **the precision artillery of semiconductor doping** — firing individual atoms into silicon with controlled depth, dose, and spatial placement that defines where every transistor turns on and off, making it the most repeated and precisely controlled step in the CMOS process flow.