ion implantation process

**Ion Implantation** is the **precision doping technique that accelerates ionized dopant atoms (boron, phosphorus, arsenic, antimony) to controlled energies (0.2 keV to 3 MeV) and embeds them into the silicon lattice at precise depths and concentrations — enabling the exacting control of transistor threshold voltage, source/drain doping, well formation, and halo profiles that define every electrical parameter of the CMOS device**. **Why Implantation Replaced Diffusion Doping** Early CMOS used gas-phase diffusion to introduce dopants into silicon — heating the wafer in a dopant-containing ambient and relying on thermal diffusion to drive atoms into the crystal. This process offered limited depth control and could not create sharp, abrupt doping profiles. Ion implantation provides independent control of dose (total atoms/cm², controlled by beam current × time) and depth (controlled by ion energy), enabling the peaked and retrograde profiles that modern devices require. **Key Parameters** - **Ion Species**: B, BF2, P, As, Sb for standard doping. C, N, Ge, In for specialty implants (amorphization, carbon co-implant for diffusion suppression, indium halo for PMOS). - **Energy**: Determines the depth of the dopant peak. Low energy (0.2-5 keV) for ultra-shallow source/drain extensions; medium energy (10-200 keV) for wells and channel doping; high energy (200 keV-3 MeV) for deep retrograde wells and buried layers. - **Dose**: The total number of ions per unit area. Ranges from 10¹¹/cm² (threshold adjust) to 10¹⁶/cm² (amorphizing source/drain). Controlled by integrating beam current over the scan area and time. - **Tilt and Twist**: The wafer is tilted 0-60° relative to the beam and rotated (twisted) to avoid channeling — the phenomenon where ions travel deep into the crystal along low-index crystallographic directions with minimal scattering, creating an unwanted deep tail in the doping profile. **Implant Damage and Annealing** Each implanted ion displaces hundreds of silicon atoms from their lattice sites, creating point defects (vacancies and interstitials) and, at high doses, amorphous zones. The crystal damage must be repaired and the dopants electrically activated by subsequent thermal annealing: - **Spike RTA**: 1000-1100°C for ~1 second. Activates dopants while limiting diffusion. - **Millisecond Anneal (MSA/LSA)**: Flash lamp or laser spike anneal at 1200-1350°C for 0.1-1 ms. Maximizes activation with near-zero diffusion — essential for ultra-shallow junction formation. **Advanced Implant Techniques** - **Plasma Doping (PLAD)**: The wafer is immersed in a dopant-containing plasma and biased to attract ions from all angles. Enables conformal doping of 3D structures (FinFET fins, nanosheet sidewalls) that line-of-sight beam implantation cannot reach. - **Hot Implant**: Wafer heated to 300-500°C during implantation. The elevated temperature promotes in-situ damage repair, preventing amorphization of SiC substrates and reducing end-of-range defects in silicon. Ion Implantation is **the surgical dopant delivery system of semiconductor fabrication** — placing exactly the right number of the right atoms at exactly the right depth to create every electrical junction, every threshold voltage, and every doping gradient in the device.