Junctionless Transistors

# Junctionless Transistors: Device Physics, Full Depletion Limits & Monolithic 3D

In classical inversion-mode MOSFETs (FinFETs and Gate-All-Around nanosheets), current modulation depends upon electrostatic inversion of a semiconductor body whose doping polarity opposes the source and drain ($n^+-p-n^+$ for nMOS, $p^+-n-p^+$ for pMOS). At sub-$3\,\text{nm}$ nodes, fabricating these metallurgical p-n junctions requires creating ultrasteep lateral doping gradients ($< 1.5\,\text{nm/decade}$) via heavy ion implantation, halo/pocket doping, and sub-millisecond laser annealing. These extreme processing steps suffer from statistical dopant straggle, transient enhanced diffusion (TED), and severe crystal defect formation.

The Junctionless Field-Effect Transistor (JLFET) eliminates physical p-n junctions entirely. A junctionless transistor consists of a single, uniformly and heavily doped semiconductor channel ($n^+-n^+-n^+$ or $p^+-p^+-p^+$, with $N_D \approx 1\times 10^{19}\text{ to }5\times 10^{19}\,\text{cm}^{-3}$) spanning from source to drain. By employing a high-work-function gate electrode wrapped around an ultra-thin channel ($T_{si} \le 5\text{ to }8\,\text{nm}$), the entire cross-section is electrostatically depleted in the OFF-state and conducts through a neutral bulk core in the ON-state, fundamentally altering device physics and eliminating high-temperature activation budgets.

Inversion-Mode MOSFET vs. Junctionless FET (JLFET) longitudinal doping profiles, transport channels, and surface vs. bulk conduction 1. INVERSION-MODE MOSFET (n⁺ - p - n⁺) Source (n⁺) Channel (p-body) Drain (n⁺) p-n Junction p-n Junction Surface Inversion Layer (< 1.5 nm) E_⊥ > 1 MV/cm Physical Mechanisms & Limitations: • Abrupt metallurgical junctions required (< 1.5 nm/dec). • Random Dopant Fluctuation (RDF) causes large σ(V_th). • Transient Enhanced Diffusion (TED) during anneals. Surface Roughness Scattering Penalty: • Inversion channel is confined to within 1–2 nm of oxide. • High transverse electric field E_⊥ pulls electrons into wall. • Severe mobility degradation (1/μ_total = 1/μ_ph + 1/μ_sr). Thermal Budget Constraints: • Requires 1000°C–1050°C spike/laser anneals for dopant activation in source/drain extensions. • Incompatible with Monolithic 3D upper tier logic (which demands thermal budget < 450°C to protect Cu). 2. JUNCTIONLESS FET (n⁺ - n⁺ - n⁺) Source (n⁺) Channel (n⁺) Drain (n⁺) ZERO METALLURGICAL JUNCTIONS (N_D ≈ 2 × 10¹⁹ cm⁻³) Bulk Neutral Core Conduction Zero Transverse E-Field (E_⊥ ≈ 0) at Flatband Operating Physics & Advantages: • Uniform, continuous doping throughout: zero junctions. • No ion implant straggle or halo doping required. • Entire body is fully depleted in OFF state by gate work function. Bulk Core Conduction Benefits: • Carriers travel down the center core of the nanowire/sheet. • Electric field perpendicular to current is nearly zero (E_⊥ ≈ 0). • Surface roughness scattering is completely eliminated! Ideal for Monolithic 3D & BEOL Logic: • Compatible with low-temp solid-phase crystallization (SPC) or laser nanosecond annealing at T < 400°C. • Allows stacking multiple logic tiers directly on top of copper interconnect BEOL layers without damage.

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## 1. Operating Physics: From Full Depletion to Bulk Neutral Conduction

The fundamental electrostatic difference between an inversion-mode MOSFET and a junctionless transistor lies in the source of mobile carriers and their spatial distribution.

In an n-channel JLFET with uniform donor concentration $N_D \approx 1\times 10^{19}\text{ to }5\times 10^{19}\,\text{cm}^{-3}$, the device transitions through three distinct electrostatic regimes as gate-to-source voltage $V_{gs}$ increases:

+----------------------------------------------------------------------------------------------------+
|                                  JLFET ELECTROSTATIC OPERATING REGIMES                             |
+--------------------+--------------------+--------------------+-------------------------------------+
| OPERATING REGIME   | GATE BIAS CONDITION| CHANNEL DEPLETION  | CARRIER TRANSPORT PHENOMENOLOGY     |
+--------------------+--------------------+--------------------+-------------------------------------+
| 1. Fully Depleted  | V_gs < V_th        | Entire channel     | Majority electrons completely       |
|    OFF-State       | (Large work-func-  | thickness T_si is  | depleted by gate work function;     |
|                    |  tion mismatch)    | fully depleted     | I_off < 10⁻¹² A/μm (subthreshold)   |
+--------------------+--------------------+--------------------+-------------------------------------+
| 2. Bulk Neutral    | V_th ≤ V_gs < V_FB | Depletion boundary | Current conducts strictly through   |
|    Core ON-State   | (Approaching flat- | shrinks; neutral   | the center of the wire; E_⊥ ≈ 0;    |
|                    |  band condition)   | bulk core opens    | zero surface roughness scattering   |
+--------------------+--------------------+--------------------+-------------------------------------+
| 3. Surface         | V_gs > V_FB        | Flatband exceeded; | Both bulk core and surface          |
|    Accumulation    | (Positive surface  | surface accumula-  | accumulation layers conduct;        |
|    Regime          |  potential ψ_s > 0)| tion layers form   | E_⊥ rises; surface scattering begins|
+--------------------+--------------------+--------------------+-------------------------------------+
JLFET Electrostatic Regimes, Band Diagrams & Transfer Scaling energy band profiles across channel thickness, depletion width shrink, and I_d–V_gs ENERGY BAND PROFILES (ACROSS T_si) -T_si/2 (Oxide) y = 0 (Center) +T_si/2 (Oxide) E_F OFF State (V_gs < V_th): Fully Depleted Flatband ON State (V_gs = V_FB): Neutral Bulk 1D Poisson Potential Distribution: d²ψ/dy² = - ( q · N_D ) / ε_si Maximum Body Thickness Criterion: T_max = 2 · W_dep = 2 · √[ (2 · ε_si · ΔΦ_ms) / (q · N_D) ] • For N_D = 2 × 10¹⁹ cm⁻³, ΔΦ_ms = 1.0 eV ⟹ T_max ≈ 5.5 nm • If T_si > T_max, center remains undepleted in OFF-state, causing catastrophic leakage current (I_off > 10⁻⁵ A/μm). • Thin channel control (T_si ≤ 5 nm) is the essential physics prerequisite! TRANSFER CHARACTERISTICS (I_d–V_gs) V_gs (V) log I_d (A/μm) V_th ≈ 0.35 V V_FB ≈ 0.70 V SS ≈ 65 mV/dec Bulk Core ON Accumulation Analytical Threshold Voltage Expression: V_th = V_FB - ( q · N_D · T_si ) / ( 2 C_ox ) - ( q · N_D · T_si² ) / ( 8 ε_si ) Work Function Matching Strategy: • Because the channel is heavily doped n⁺, V_th would normally be negative (depletion mode / normally-ON). • To achieve normally-OFF enhancement mode (V_th ≈ +0.35 V): Gate metal must have high work function (Φ_m ≥ 5.1 eV, such as Pt, Ru, or p-type work function TiN/TaN). • I_on/I_off ratio exceeds 10⁷ with excellent short-channel immunity.

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## 2. Quantitative Electrostatics: The $T_{max}$ Depletion Condition

To achieve acceptable static power dissipation in logic circuits ($I_{off} < 10^{-11}\,\text{A}/\mu\text{m}$), the gate must fully deplete all free carriers across the channel cross-section at $V_{gs} = 0\,\text{V}$.

### 2.1 1D Poisson Equation Across the Semiconductor Film
Consider a double-gate or cylindrical nanosheet junctionless transistor with uniform donor concentration $N_D$ and thickness $T_{si}$, bounded by gate oxide capacitance $C_{ox}$.

Integrating the 1D Poisson equation from the channel center ($y = 0$) to the silicon/oxide interface ($y = T_{si}/2$):

$$\frac{d^2 \psi(y)}{dy^2} = -\frac{q N_D}{\epsilon_{si}}$$

Applying boundary conditions at the center plane (by symmetry, zero vertical electric field $d\psi/dy|_{y=0} = 0$):

$$\psi(y) = \psi(0) - \frac{q N_D y^2}{2 \epsilon_{si}}$$

The electrostatic potential drop from the surface to the center is:

$$\Delta \psi_{si} = \psi\left(\frac{T_{si}}{2}\right) - \psi(0) = -\frac{q N_D T_{si}^2}{8 \epsilon_{si}}$$

### 2.2 Maximum Body Thickness Formula ($T_{max}$)
For full channel pinch-off in the OFF-state, the gate depletion region $W_{dep}$ from both top and bottom interfaces must merge at the channel center ($2 W_{dep} \ge T_{si}$):

$$T_{max} = 2 \sqrt{\frac{2 \epsilon_{si} (\Phi_m - \Phi_{si})}{q N_D}}$$

Where:
- $\epsilon_{si} \approx 11.7 \times 8.854 \times 10^{-14}\,\text{F/cm} = 1.036 \times 10^{-12}\,\text{F/cm}$.
- $\Phi_m - \Phi_{si} \approx 1.0\text{ to }1.2\,\text{eV}$ is the gate-to-channel work-function difference.
- $N_D = 2.0 \times 10^{19}\,\text{cm}^{-3}$ is the uniform donor concentration.

Evaluating numerically:

$$T_{max} = 2 \sqrt{\frac{2 \times (1.036 \times 10^{-12}\,\text{F/cm}) \times (1.0\,\text{V})}{(1.602 \times 10^{-19}\,\text{C}) \times (2.0 \times 10^{19}\,\text{cm}^{-3})}} \approx \mathbf{5.1\,\text{nm}}$$

This fundamental scaling law proves that body thickness must be engineered below $5\text{ to }6\,\text{nm}$. If the nanowire or nanosheet thickness exceeds $T_{max}$, the gate field cannot penetrate to the center of the wire, leaving a permanent conductive neutral filament that drives OFF-state leakage current above microamps per micrometer.

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## 3. Threshold Voltage & Work-Function Matching

Because the channel is heavily doped n-type, the transistor would naturally behave as a normally-ON (depletion-mode) device if paired with a midgap or n-type gate metal ($\Phi_m \approx 4.1\text{ to }4.3\,\text{eV}$).

To shift the threshold voltage into positive territory ($V_{th} \approx +0.35\,\text{V}$) for CMOS logic:

$$V_{th} = V_{FB} - \frac{q N_D T_{si}}{2 C_{ox}} - \frac{q N_D T_{si}^2}{8 \epsilon_{si}}$$

Where the flatband voltage is given by the work-function difference:

$$V_{FB} = \Phi_{ms} = \frac{\Phi_m - \chi_{si}}{q} - \frac{k_B T}{q} \ln\left(\frac{N_D}{n_i}\right)$$

### 3.1 Gate Work-Function Engineering
To achieve a positive $V_{th} \approx +0.35\,\text{V}$ with $T_{si} = 5\,\text{nm}$, $EOT = 0.8\,\text{nm}$ ($C_{ox} \approx 4.3 \times 10^{-6}\,\text{F/cm}^2$), and $N_D = 2 \times 10^{19}\,\text{cm}^{-3}$:
1. Depletion charge term across oxide:

$$\frac{q N_D T_{si}}{2 C_{ox}} = \frac{1.602 \times 10^{-19} \times 2 \times 10^{19} \times 5 \times 10^{-7}}{2 \times 4.3 \times 10^{-6}} \approx 0.186\,\text{V}$$

2. Depletion potential drop across silicon:

$$\frac{q N_D T_{si}^2}{8 \epsilon_{si}} = \frac{1.602 \times 10^{-19} \times 2 \times 10^{19} \times (5 \times 10^{-7})^2}{8 \times 1.036 \times 10^{-12}} \approx 0.097\,\text{V}$$

3. Total required flatband shift:

$$V_{FB} = V_{th} + 0.186\,\text{V} + 0.097\,\text{V} = 0.35\,\text{V} + 0.283\,\text{V} \approx \mathbf{+0.63\,\text{V}}$$

To establish $V_{FB} \approx +0.63\,\text{V}$ on heavily n-doped silicon ($\Phi_{si} \approx 4.1\,\text{eV}$), the gate metal must exhibit an effective work function of:

$$\Phi_m = \Phi_{si} + q V_{FB} \approx 4.1\,\text{eV} + 0.63\,\text{eV} \ge \mathbf{4.73\text{ to }5.10\,\text{eV}}$$

Foundries achieve this using p-type work-function metals such as platinum (Pt), ruthenium (Ru), or aluminum-depleted ALD titanium nitride ($\text{TiN}$).

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## 4. Bulk Core Conduction vs. Surface Roughness Scattering

The primary transport benefit of junctionless transistors in the ON-state ($V_{th} \le V_{gs} \le V_{FB}$) is the complete elimination of the transverse electric field:

$$\mathcal{E}_\perp(y) = -\frac{d\psi}{dy} \approx 0 \quad \text{at } V_{gs} \approx V_{FB}$$

In classical inversion-mode MOSFETs, electrons are clamped against the $\text{Si}/\text{SiO}_2$ dielectric interface by transverse fields exceeding $\mathcal{E}_\perp > 1.0\,\text{MV/cm}$. According to Matthiessen's rule:

$$\frac{1}{\mu_{total}} = \frac{1}{\mu_{coulomb}} + \frac{1}{\mu_{phonon}} + \frac{1}{\mu_{surface\_roughness}}$$

Surface roughness scattering scales aggressively with transverse field ($\mu_{sr} \propto \mathcal{E}_\perp^{-2}$). In inversion-mode devices, this degradation slashes room-temperature mobility down to $\mu_{eff} < 80\text{ to }120\,\text{cm}^2/\text{V}\cdot\text{s}$.

In junctionless transistors operating in the bulk core regime, electrons travel through the center of the silicon crystal without interacting with the dielectric interface. Consequently, surface roughness scattering is eliminated, and carrier mobility approaches the bulk ionized-impurity-limited mobility:

$$\mu_{bulk} \approx \mathbf{180\text{ to }240\,\text{cm}^2/\text{V}\cdot\text{s}}$$

Delivering up to $2\times$ higher drive current density per cross-sectional area compared to sub-$3\,\text{nm}$ inversion-mode nanosheets.

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## 5. Thermal Budget Simplification for Monolithic 3D Integration

The absence of metallurgical junctions makes the JLFET the premier transistor architecture for Monolithic 3D (Sequential 3D) integration and back-end-of-line (BEOL) logic tiers:

1. Elimination of $1000^\circ\text{C}$ Junction Activation Anneals: Inversion-mode devices require high-temperature spike or laser annealing to activate source/drain extension implants without excessive diffusion. This exceeds the thermal budget of underlying copper/low-k interconnects ($T_{max} \le 400^\circ\text{C}\text{ to }450^\circ\text{C}$).
2. In Situ Doped Deposition: Junctionless channels can be deposited via low-temperature ALD or PECVD with in situ phosphorus or boron doping already uniform throughout the film.
3. Solid-Phase Crystallization (SPC): The amorphous silicon channel is crystallized into single-crystal or high-mobility polysilicon using nanosecond green laser annealing ($532\,\text{nm}$) or low-temperature furnace anneals ($T \le 400^\circ\text{C}$ for $2\,\text{hours}$), preserving all underlying copper interconnects and dielectric layers with zero thermal degradation.

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