Latch

A latch is a one-bit memory circuit built from logic gates that is level-sensitive: while its enable signal is active, its output continuously follows its input in real time, and the instant the enable signal deactivates, the output freezes and holds whatever value it last saw. This continuous-tracking-then-freezing behavior is what separates a latch from a flip-flop, which only samples its input at a single clock edge rather than tracking it for an entire window — a distinction that sounds minor but has real consequences for how safely each one can be used in a chip's timing. How a latch actually tracks and then holds a value looks like this:

A few things are worth knowing about why a latch's continuous tracking makes it a fundamentally different tool from a flip-flop, not just a simpler version of one:

A latch is transparent for an entire window of time, while a flip-flop captures at a single instant, and that difference is exactly why a latch is risky to use directly as a pipeline boundary. During the window a latch's enable signal is active, its output isn't a stable, settled value — it's a live, continuously updating mirror of whatever the input is doing at that moment, including any glitches or multiple transitions that occur during that window. If combinational logic feeding a latch's input is still settling when the enable window is open, that instability can pass straight through to the latch's output and onward to the next stage, a failure mode called a race condition. A flip-flop avoids this entirely by only looking at its input for a vanishingly brief instant at the clock edge, ignoring everything that happens before or after — which is exactly why flip-flops, not bare latches, are the default choice for pipeline stage boundaries in nearly all digital chip design.

A latch isn't a lesser version of a flip-flop that chip designers avoid out of caution — it's a genuinely useful, often smaller and faster building block in its own right, and it's the literal internal component a flip-flop is built from. A single latch typically needs fewer transistors than a full flip-flop, because a flip-flop's edge-triggered behavior comes specifically from chaining two latches master-slave, with one transparent while the other holds, alternating on opposite clock phases. That smaller transistor count and shorter internal delay path is exactly why latch-based design, sometimes called latch-based or multi-phase clocking, remains attractive in specific high-performance or area-constrained parts of a chip where engineers are willing to take on the added timing analysis complexity in exchange for real area and speed gains — it's a deliberate tradeoff, not a beginner's mistake.

Level-sensitive timing analysis is fundamentally harder than edge-triggered timing analysis, and that added difficulty is the real-world cost that keeps most chip design defaulting to flip-flops rather than latches. Because a latch's output can still be changing anywhere within its transparent window, verifying that a latch-based design meets timing requires reasoning about an entire window of possible input arrival times rather than checking against one well-defined clock edge, a technique called time borrowing, where a signal arriving late in one latch's window can "borrow" settling time from the next stage. This is powerful when used correctly — it can relax tight timing paths that a pure flip-flop design couldn't accommodate — but it demands far more careful, specialized static timing analysis tooling and expertise, which is exactly why mainstream digital design defaults to simpler, more predictable flip-flops unless a design specifically needs the area or speed a latch-based approach can offer.

An SR latch, built from just two cross-coupled NOR or NAND gates, is the simplest possible version of this idea and the one most often used to introduce the concept, even though it has a known failure mode that more refined latch designs exist specifically to fix. Cross-coupling two gates so each one's output feeds the other's input creates a circuit with two valid stable states, which is the most basic form of digital memory achievable from logic gates alone — apply a set input and the latch locks into one state, apply a reset input and it locks into the other. The well-known problem is that applying both the set and reset inputs simultaneously drives the circuit into an undefined or unstable condition, which is precisely the failure mode that more developed latch types, like the gated D latch used inside real flip-flops, are built to eliminate by construction rather than by rule-of-thumb avoidance.

Read a latch as a transparent window, not a simplified flip-flop: it tracks its input continuously while enabled and only freezes when that window closes, a behavior that's genuinely risky to leave exposed at a pipeline boundary but genuinely valuable when deliberately exploited through time-borrowing — and understanding that tradeoff, area and speed against timing-analysis complexity, is what separates knowing when to reach for a latch from simply defaulting to a flip-flop out of habit.