Layout Editor
A layout editor is the software tool used to create and manipulate the physical geometry of an integrated circuit — the actual shapes on each layer that define where transistors, wires, and contacts go — at the level of the polygons that will become the chip's photomasks. It is the tool where the abstract logic of a design meets its concrete physical realization, the place where a designer or an automated tool draws and edits the precise geometric patterns that fabrication will reproduce in silicon. The layout editor is a core piece of the electronic design automation toolset, sitting at the physical-design end of the flow.
The layout editor operates at the level of geometry and layers, which is what distinguishes it from tools that work with logic or behavior. A chip is built from many layers, each patterned with shapes that define features such as diffusion regions, gates, metal wires, and the contacts connecting layers. The layout editor lets a user view and edit these shapes layer by layer, placing and adjusting the polygons that, when fabricated, become the physical structures of the chip. Where a logic tool deals in gates and signals, the layout editor deals in rectangles and polygons on specific layers, making it the tool concerned with the literal physical form of the circuit.
The layout editor is where a design's physical form is created, whether drawn by hand for custom work or generated by automated tools and then inspected or adjusted. In fully custom design, an engineer uses the layout editor to draw the geometry directly, placing each shape with care; in automated flows, placement-and-routing tools produce the layout, which can then be viewed and refined in the editor. Either way, the layout editor is the window onto the chip's actual geometry, and it is where the final physical description takes shape before it is checked and converted into the data that drives manufacturing.
The layout editor works hand in hand with design-rule checking, because the geometry it produces must satisfy the manufacturability constraints of the process. As geometry is drawn or edited, it must obey the minimum widths, spacings, and overlaps of the process design rules, and a design-rule-check tool verifies this, flagging violations for correction. The layout editor and the rule checker form a tight loop: the editor creates and modifies geometry, and the checker ensures that geometry is legal. This coupling is essential, since a beautiful layout that violates the rules cannot be manufactured.
The layout editor embodies the physical-design layer of chip creation, the point where logical intent becomes literal silicon geometry, and it illustrates how chip design spans multiple levels of abstraction. A complete design flow moves from behavior to logic to physical layout, and the layout editor is the tool for that final, most concrete level. Understanding it clarifies that designing a chip is not only about deciding what the circuit should do but ultimately about specifying exact shapes on exact layers, and the layout editor is where that specification is made and manipulated.
Read the layout editor as the drafting table for silicon geometry: the tool where a chip's design becomes literal shapes on literal layers, whether drawn by hand or produced by automation, working in a tight loop with design-rule checking to turn logical intent into the manufacturable polygons that become the photomasks.