lightly doped drain LDD
**LDD (Lightly Doped Drain) and Spacer Formation** is the **CMOS process sequence that creates a graded doping profile at the source/drain edges through self-aligned implantation and dielectric spacer patterning**, reducing the peak electric field at the drain junction to suppress hot carrier injection (HCI) and short-channel effects — a fundamental transistor engineering technique used at every CMOS technology node.
**The Hot Carrier Problem**: Without LDD, the abrupt junction between heavily doped drain and channel creates an intense electric field at the drain edge. Energetic ("hot") carriers gain enough energy to: inject into the gate oxide (causing threshold voltage shift and degradation over time), generate electron-hole pairs via impact ionization (causing substrate current), and create interface traps (reducing mobility). LDD spreads the voltage drop over a longer distance, reducing peak field.
**LDD/Spacer Process Sequence**:
| Step | Process | Purpose |
|------|---------|--------|
| 1. Gate patterning | Define gate on gate oxide | Self-alignment reference |
| 2. LDD implant | Low-dose, low-energy implant (N+: P/As, P+: B/BF₂) | Create lightly doped extension |
| 3. Halo implant | Angled implant of opposite type (P+: As, N+: B) | Suppress punchthrough |
| 4. Spacer deposition | Conformal SiN or SiO₂/SiN stack (LPCVD/PECVD) | Build spacer material |
| 5. Spacer etch | Anisotropic RIE leaving sidewall spacer | Define spacer width |
| 6. S/D implant | High-dose, higher-energy implant (N+: As/P, P+: B) | Create deep S/D junctions |
| 7. Activation anneal | RTA or spike anneal (1000-1100°C) | Activate dopants |
**Spacer Engineering**: The spacer width (15-30nm at advanced nodes) determines the offset between the LDD edge (aligned to gate) and the deep S/D junction (aligned to gate + spacer). Multiple spacer types exist: **single spacer** (one SiN layer), **dual spacer** (SiO₂ liner + SiN main spacer), and **triple spacer** (for additional process flexibility). The spacer also serves as a mask for selective S/D epitaxy and silicide formation.
**Halo (Pocket) Implant**: An angled implant (7-30° tilt, rotating wafer) of the OPPOSITE doping type, creating a localized high-doping region ("pocket") beneath the LDD extension. The halo: increases the effective channel doping near the source/drain edges, raising the threshold voltage roll-off curve; suppresses drain-induced barrier lowering (DIBL) by increasing the barrier between source and drain at short channel lengths; and enables threshold voltage targeting independent of channel length (reducing V_th variability).
**Advanced Node Evolution**: At FinFET and GAA nodes, the concepts persist but implementation changes: LDD-equivalent extensions are formed by conformal implant or plasma doping on the fin/sheet sidewalls; spacers become multi-layered stacks with air gaps (low-k spacers to reduce parasitic capacitance); and inner spacers in GAA devices serve the additional role of isolating the gate from S/D epitaxy in the inter-sheet regions. The fundamental physics (field reduction, short-channel control) remains unchanged.
**LDD and spacer formation exemplify the principle of self-aligned process integration — where the gate structure serves as both the functional device element and the alignment reference for junction engineering, enabling the precise doping profiles that control every aspect of transistor electrical behavior from threshold voltage to reliability.**