spacer formation process

**Spacer Formation** is the **conformal deposition and anisotropic etch-back process that creates thin dielectric sidewall structures (Si3N4, SiO2, or SiCO, 3-10 nm thick) on the vertical edges of gate electrodes and mandrels — serving multiple critical functions: protecting the gate edge during source/drain implant and epitaxy, defining the offset between the gate and the S/D junction, providing self-aligned contact etch selectivity, and enabling self-aligned multi-patterning for sub-lithographic feature definition**. **Gate Spacer Functions** 1. **S/D Offset Spacer**: The spacer width defines the lateral distance between the gate edge and the heavily-doped source/drain region. This offset prevents the S/D junction from extending under the gate (which would increase overlap capacitance and reduce effective channel length). 2. **Implant/Epitaxy Mask**: During S/D epitaxy or implantation, the spacer protects the gate sidewall and channel region from direct dopant or epitaxial exposure. 3. **SAC (Self-Aligned Contact) Etch Stop**: During contact etch, the nitride spacer protects the gate from being exposed. The contact etch removes oxide but stops on the nitride spacer and gate cap, inherently self-aligning the contact to the S/D region. 4. **Stress Engineering**: CESL (Contact Etch Stop Liner) deposited conformally over the gate and spacer applies tensile (NMOS) or compressive (PMOS) stress to the channel, enhancing carrier mobility. **Spacer Process Flow** 1. **Conformal Deposition**: ALD or LPCVD deposits a uniform Si3N4 film (3-10 nm) over the entire wafer, conformally coating the top and sidewalls of the gate and the flat field regions. 2. **Anisotropic Etch-Back**: A highly anisotropic plasma etch (CHF3/CH2F2/O2/Ar) removes the film from all horizontal surfaces (field, gate top) while preserving the film on vertical surfaces (gate sidewalls). The etch chemistry and ion bombardment directivity must be precisely controlled to leave a clean, uniform spacer with no residual film ("footer") at the base. 3. **Multi-Spacer Architectures**: Advanced nodes use multiple spacer layers — a thin L-shaped inner spacer (offset spacer for lightly-doped drain), a thicker main spacer (for S/D implant/epi offset), and sometimes an outer spacer for additional offset control. Each layer requires its own deposition and etch-back. **Spacers for Multi-Patterning (SADP)** Beyond transistor formation, spacer technology is the foundation of Self-Aligned Double Patterning: 1. A mandrel line is patterned at 2x the target pitch. 2. A conformal spacer is deposited on the mandrel sidewalls. 3. The mandrel is selectively removed, leaving free-standing spacer lines at half the mandrel pitch. 4. These spacer lines serve as the etch mask for the underlying layer. This technique, repeated twice (SAQP), achieves features at quarter-pitch — enabling sub-20nm features with 193nm immersion lithography. Spacer Formation is **the most versatile sidewall process in semiconductor manufacturing** — simultaneously serving as junction controller, self-alignment enabler, stress engineer, and multi-patterning workhorse across every device architecture from planar CMOS to GAA nanosheets.