liner deposition cmos

**Liner Deposition** is the **thin film deposited on via and trench sidewalls and bottoms before filling with metal** — providing adhesion, diffusion barrier, and nucleation functions that ensure reliable metal interconnect formation. **Why Liners Are Needed** - Copper diffuses rapidly through SiO2 and Si → kills transistors. - Tungsten doesn't adhere to SiO2 directly → delamination. - Liners provide: diffusion barrier (Cu), adhesion (W), nucleation surface for CVD/ELD. **Contact Liner (W Contacts)** **Ti Adhesion Layer**: - PVD Ti, 5–20nm. - Reacts with Si at contact bottom: Ti + Si → TiSi2 (lowers contact resistance). - Provides adhesion for TiN above. **TiN Barrier Layer**: - CVD or PVD TiN, 10–30nm. - Diffusion barrier: Prevents W from reacting with Si. - Nucleation layer: CVD W nucleates uniformly on TiN (poor on SiO2). **Copper Via/Trench Liner (Dual Damascene)** **TaN Diffusion Barrier**: - ALD or iPVD TaN, 2–4nm at advanced nodes. - Excellent Cu diffusion barrier: Activation energy > 1.5 eV. - Must be conformal in high-AR features (AR > 10:1). **Cu Seed Layer**: - PVD Cu, 10–50nm — nucleation layer for Cu electroplating. - Must be continuous even at bottom corners — gap-fill challenge. - At 5nm node: Seed may be replaced by fully-CVD or ALD Cu. **Scaling Challenge** - At 5nm node: TaN + Cu seed = 5–8nm of overhead in a 10nm-wide trench. - Alternative barriers: Co, Ru metal barriers (< 2nm effective) — enable thinner liners. - Ruthenium liner: Direct-plate without Cu seed, better resistivity, thinner possible. Liner deposition is **a critical integration challenge at each technology node** — balancing barrier effectiveness with the overhead cost of film thickness becomes increasingly difficult as feature sizes approach single-digit nanometers.