Load Pull Measurement
# Load-Pull Measurement: Find the Load a Power Amplifier Needs
Load pull maps a power amplifier’s large-signal behavior while the impedance at its output is deliberately varied. It answers a practical chip-design question: which load should the output matching network present to the transistor for the required power, efficiency and linearity?
A transistor is not inherently optimized for a 50-ohm load at its device terminals. The external system may use 50 ohms, while a matching network transforms that impedance to the value the transistor needs. Near compression, small-signal S-parameters alone cannot describe the resulting nonlinear behavior.
## 1. Follow the measurement path
*Simplified passive load-pull path. Actual benches add directional couplers, calibrated receivers, bias networks and protection. The source impedance must also be controlled; varying it is called source pull.*
For each chosen frequency, bias and input-drive condition, sweep the load reflection coefficient in amplitude and phase. At every point, measure delivered RF power, input power and DC consumption. For modulated signals, also evaluate error vector magnitude (EVM) and adjacent-channel leakage ratio (ACLR). Record these conditions with the results: a load that works at one drive level may be unsuitable at another.
## 2. Read the contours as tradeoffs
*Conceptual contour illustration, not measured data. Curves connect equal metric values; the blue and green centers illustrate different candidate optima. Actual contours can be irregular, and their values must come from a calibrated sweep.*
The load reflection coefficient is ΓL = (ZL − Z₀)/(ZL + Z₀) for a real reference impedance Z₀, commonly 50 ohms. ΓL = 0 is a matched load; the unit circle bounds passive loads. This drawing uses Cartesian Γ coordinates rather than a full Smith-chart impedance grid.
Power-added efficiency is PAE = (Pout − Pin)/PDC × 100%. Use linear power units and consistent reference planes. For example, Pout = 1 W, Pin = 0.1 W and PDC = 2 W gives 45% PAE; drain efficiency would be 50%. PAE subtracts input RF power and therefore differs from drain efficiency.
The highest-power load, highest-PAE load and best-linearity load need not coincide. Choose an acceptable region with margin, then synthesize a matching network that can reach it over bandwidth and manufacturing variation. Include network loss when translating device-plane results into system performance.
## 3. Choose the right kind of load pull
| Method | How it changes the load | Main limitation to check |
|---|---|---|
| Passive | Mechanical or electronic impedance tuner | Fixture loss restricts achievable reflection at the DUT |
| Active | Phase-coherent injected wave controls the effective load | Calibration, injected-power capacity and stability |
| Harmonic | Controls terminations at the fundamental and selected harmonics | Each harmonic impedance and reference plane must be known |
Harmonic terminations change the voltage and current waveforms at the transistor and can alter efficiency and device stress. A favorable fundamental-frequency contour is not proof that the harmonic environment is safe. Active and passive techniques can also be combined in a hybrid bench.
## 4. Make the map useful for chip design
Calibrate at the device reference plane. Cables, probes, fixtures and bias networks introduce loss and phase shift. De-embed their effects so the reported load and power correspond to the intended transistor or package plane. Do not mix intrinsic-device, package and connector impedances in one design decision.
Track heat and operating history. Repeat measurements under controlled thermal conditions. Pulsed testing can reduce self-heating, but duty cycle and pulse width must be recorded; a pulsed optimum is not automatically a continuous-wave optimum.
Check stability and stress throughout the sweep. Some impedances may cause oscillation, excessive voltage swing or current. Set measurement limits for the device and bench, and distinguish an intentionally varied load from an uncontrolled unstable operating point.
Validate the implemented network. Recheck output power, PAE, EVM and ACLR at the intended signal bandwidth and output backoff. Measure mismatch tolerance separately across the required load region. The contour map guides the design; the finished amplifier still needs verification.
Load pull is a deliberate impedance sweep used to characterize an amplifier. VCO pulling describes an oscillator frequency disturbance, while injection locking describes synchronization by an injected periodic signal. The similar terminology refers to different mechanisms.
## References
- [Rohde & Schwarz: Amplifier characterization using load pull](https://www.rohde-schwarz.com/uk/applications/amplifier-characterization-using-load-pull_56279-922304.html) — measurement topology, reference planes and active/passive methods.
- [Keysight: RF Circuit Design Techniques for Power Amplifier Load Pull](https://www.keysight.com/dk/en/learn/course.rf-circuit-design-techniques-for-power-amplifier-load-pull.html) — applying measured data to power, efficiency and modulation quality.