local interconnect
**Local Interconnect (M0 / LI)** is the **lowest metal layer that provides short-range wiring within a standard cell** — connecting transistor contacts to each other and to Via-0 without using the first global metal layer (M1), reducing M1 congestion and enabling more compact cell layouts at advanced nodes.
**What Local Interconnect Does**
- **Connects**: Source/drain contacts to gate contacts within the same cell.
- **Routes**: Simple intra-cell connections (e.g., connect NMOS drain to PMOS drain in an inverter).
- **Decouples**: Cell-internal routing from inter-cell global routing on M1.
**Why Local Interconnect Was Introduced**
- At older nodes (28nm+): M1 handled both intra-cell and inter-cell routing — manageable.
- At 14nm and below: Cell pin density increases, M1 becomes severely congested.
- Adding M0 as a dedicated intra-cell routing layer frees M1 for inter-cell signal routing.
**Local Interconnect Implementation**
| Node | LI Material | Pitch | Process |
|------|------------|-------|---------|
| Intel 10nm | Cobalt (Co) | ~36 nm | Subtractive |
| TSMC 7nm | Tungsten (W) | ~40 nm | Damascene |
| Samsung 5nm | Ruthenium (Ru) | ~28 nm | Subtractive |
| Intel 18A | Ruthenium (Ru) | ~22 nm | Subtractive |
**Subtractive vs. Damascene M0**
- **Damascene** (TSMC): Trench etch in dielectric → barrier + seed → Cu/W fill → CMP. Standard but limited by barrier thickness at tight pitches.
- **Subtractive** (Intel, Samsung): Deposit metal blanket → etch metal into lines. No barrier needed inside features — maximum conductor volume. Works best with etch-friendly metals (Ru, Mo).
**Impact on Cell Design**
- **Bidirectional M0**: Some implementations allow both horizontal and vertical M0 routing within the cell — more flexible cell architecture.
- **Unidirectional M0**: Simpler design rules but fewer routing options.
- **Dual-M0 (M0A + M0B)**: Two local interconnect sub-layers at orthogonal angles — maximum intra-cell connectivity.
**Routing Resources per Cell**
- M0: 2-4 tracks per cell (intra-cell only).
- M1: 4-6 tracks per cell (inter-cell signal routing).
- M2: Power rail (Vdd, Vss) + signal routing.
Local interconnect is **essential infrastructure for dense standard cells at advanced nodes** — by handling intra-cell wiring at the lowest metal level, it relieves the routing pressure on M1 and enables the continued cell height scaling that drives logic density improvements.