logic bist
**Logic BIST (LBIST)** is the **on-chip built-in self-test mechanism that generates test patterns and analyzes responses internally** — eliminating the need for expensive external automatic test equipment (ATE) to generate and apply test vectors for manufacturing testing, reducing test time and cost while enabling at-speed testing that external testers cannot support.
**How LBIST Works**
1. **PRPG (Pseudo-Random Pattern Generator)**: LFSR (Linear Feedback Shift Register) generates pseudo-random test patterns.
2. **Pattern Application**: Patterns driven into the scan chains through the logic under test.
3. **Response Capture**: Outputs captured in scan chains after each pattern.
4. **MISR (Multiple-Input Signature Register)**: Compresses all responses into a single signature (hash).
5. **Pass/Fail**: Final MISR signature compared against expected golden signature.
- Match → PASS (chip is good).
- Mismatch → FAIL (defect detected).
**LBIST Architecture**
| Component | Function | Implementation |
|-----------|----------|--------------|
| BIST Controller | Sequences test modes, counts patterns | Small FSM |
| PRPG | Generates pseudo-random patterns | LFSR (16-32 bits) |
| Phase Shifter | Decorrelates patterns for spatial variation | XOR network |
| Scan Chains | Shift patterns through logic | Standard DFT scan |
| MISR | Compresses output signature | Parallel LFSR |
**LBIST vs. External Test (ATPG)**
| Aspect | External ATPG | LBIST |
|--------|--------------|-------|
| Pattern Source | ATE (external tester) | On-chip LFSR |
| Test Speed | Limited by ATE pin speed | At-speed (full clock frequency) |
| Fault Coverage | 97-99% (optimized) | 90-95% (random patterns) |
| ATE Cost | $5-50M per tester | Minimal (on-chip) |
| Test Time per Chip | 1-10 seconds | 0.1-1 seconds |
| Pattern Count | 1K-10K (targeted) | 10K-1M (brute force) |
**Improving LBIST Coverage**
- **Test Points**: Insert controllability/observability points at hard-to-test nodes.
- **Weighted PRPG**: Bias random patterns toward values that exercise hard faults.
- **Hybrid BIST**: LBIST for bulk testing + small set of deterministic ATPG patterns for remaining coverage.
**At-Speed Testing**
- LBIST runs at the chip's actual operating frequency — detects timing-dependent defects (small-delay faults) that slow ATE testing misses.
- Launch-on-shift and launch-on-capture modes test both combinational and sequential paths.
Logic BIST is **increasingly essential as chip complexity grows** — for billion-gate SoCs where ATE test time and pattern storage would be prohibitive, LBIST provides fast, low-cost manufacturing test that catches defects at real operating speeds.