memory bist architecture

**Memory BIST (Built-in Self-Test) Architecture** is **the on-chip test infrastructure that autonomously generates test patterns, applies them to embedded memories, analyzes results, and identifies failing cells for repair — enabling manufacturing test of thousands of SRAM/ROM instances without external tester pattern storage**. **MBIST Controller Architecture:** - **Controller FSM**: state machine sequences through test algorithms, managing address generation, data pattern selection, read/write operations, and comparison — single controller can test multiple memory instances sequentially or in parallel - **Address Generator**: produces sequential, inverse, and random address sequences required by March algorithms — column-march and row-march modes exercise word-line and bit-line decoders independently - **Data Background Generator**: creates test data patterns including all-0s, all-1s, checkerboard, inverse-checkerboard, and diagonal patterns — data-dependent faults (coupling faults between adjacent cells) require specific pattern combinations - **Comparator and Fail Logging**: read data compared against expected pattern — failing addresses stored in on-chip BIRA (Built-in Redundancy Analysis) registers for repair mapping **March Test Algorithms:** - **March C- Algorithm**: industry standard 10N complexity algorithm covering stuck-at, transition, coupling, and address decoder faults — sequence: ⇑(w0); ⇑(r0,w1); ⇑(r1,w0); ⇓(r0,w1); ⇓(r1,w0); ⇑(r0) where ⇑=ascending, ⇓=descending - **March B Algorithm**: 17N complexity with improved coverage for linked coupling faults — more thorough but 70% longer test time than March C- - **Checkerboard Test**: detects pattern-sensitive faults and cell-to-cell leakage — writes alternating 0/1 patterns and reads back, then inverts and repeats - **Retention Test**: writes pattern, waits programmable duration (1-100 ms), then reads — detects cells with marginal data retention due to weak-cell leakage or poor SRAM stability **Repair Analysis (BIRA):** - **Redundancy Architecture**: memories include spare rows and columns — typical 256×256 SRAM has 4-8 spare rows and 2-4 spare columns activatable by blowing eFuses - **Repair Algorithm**: BIRA logic determines optimal assignment of failing cells to spare rows/columns — NP-hard problem approximated by greedy allocation heuristics - **Repair Rate**: percentage of memories made functional through redundancy — target >99% repair rate for large memories to avoid yield loss - **Fuse Programming**: repair information stored in eFuse or anti-fuse arrays — programmed during wafer sort and verified at final test **Memory BIST is essential for modern SoC manufacturing test — with embedded SRAM consuming 40-70% of die area, untestable memory defects would dominate yield loss without comprehensive BIST coverage.**