memory bist
**Memory BIST (Built-In Self-Test)** is the **on-chip test infrastructure that autonomously generates test patterns, applies them to embedded memories (SRAM, ROM, register files), and analyzes results to detect manufacturing defects** — eliminating the need for expensive external ATE memory testing, reducing test time from minutes to milliseconds, and enabling memory repair through redundant row/column activation, with MBIST being mandatory for any chip containing more than a few kilobytes of embedded memory.
**Why Memory Needs Special Testing**
- Modern SoCs: 50-80% of die area is SRAM and other memories.
- Memory is the densest structure → most susceptible to manufacturing defects.
- Defect types: Stuck-at faults, coupling faults, address decoder faults, retention faults.
- External ATE testing: Too slow for Gb-scale embedded memory → BIST tests at-speed from inside.
**MBIST Architecture**
```
MBIST Controller
/ | \
Pattern Comparator Repair
Generator Logic Analysis
| | |
v v v
[Memory Under Test (MUT)]
Write Port → SRAM Array → Read Port
```
- **Pattern generator**: Produces addresses and data patterns (March algorithms).
- **Comparator**: Checks read data against expected values.
- **Repair analysis**: Logs failing addresses → determines optimal row/column replacement.
- **Controller FSM**: Sequences the entire test without external intervention.
**March Test Algorithms**
| Algorithm | Pattern | Complexity | Fault Coverage |
|-----------|---------|-----------|----------------|
| March C- | ⇑(w0); ⇑(r0,w1); ⇑(r1,w0); ⇓(r0,w1); ⇓(r1,w0); ⇑(r0) | 10N | Stuck-at, transition, coupling |
| March SS | Extended March C- | 22N | + Address decoder faults |
| March LR | March with retention delay | 10N + delay | + Retention faults |
| MATS+ | ⇑(w0); ⇑(r0,w1); ⇓(r1,w0) | 5N | Basic stuck-at |
- N = number of memory addresses. ⇑ = ascending address. ⇓ = descending.
- March C-: Industry standard — good fault coverage at reasonable test time.
**Memory Repair**
- **Redundant rows/columns**: Extra rows and columns built into SRAM array.
- **Repair flow**: MBIST identifies failing cells → repair analysis determines if repairable → fuse/anti-fuse programs replacement.
- If 3 failing rows and 4 spare rows → repairable.
- If failing rows span more than available spares → die is scrapped.
- **Repair analysis algorithms**: Optimal assignment of spare rows/columns to maximize yield.
- Bipartite matching, greedy allocation, or exhaustive search for small repair budgets.
**MBIST Integration in Design Flow**
1. Memory compiler generates SRAM instance.
2. MBIST tool (Synopsys DFT Compiler, Cadence Modus) wraps each memory with BIST logic.
3. RTL simulation verifies BIST patterns detect injected faults.
4. Synthesis + P&R includes BIST controller and repair fuse logic.
5. On ATE: Trigger MBIST → collect pass/fail → program repair fuses → retest.
**Test Time Savings**
| Method | Test Time for 1MB SRAM | Cost |
|--------|----------------------|------|
| External ATE pattern | ~100 ms | High (ATE time expensive) |
| MBIST at-speed | ~1 ms | Low (self-contained) |
| MBIST retention test | ~10 ms (incl. pause) | Low |
Memory BIST is **the enabling technology for economically viable embedded memory testing** — without MBIST, the test cost of the gigabytes of SRAM in modern SoCs would exceed the manufacturing cost of the silicon itself, and the yield-saving memory repair that MBIST enables would be impossible, making MBIST one of the highest-ROI design investments in the entire chip development process.