memory bist
**Memory BIST (MBIST)** is the **on-chip test infrastructure that automatically tests embedded SRAM, ROM, and register file arrays using algorithmic march patterns** — essential because memories occupy 60-80% of modern SoC die area and cannot be tested effectively by logic scan chains, requiring specialized pattern sequences to detect cell failures, address decoder faults, and coupling defects.
**Why MBIST?**
- Memories have regular array structures — random scan patterns don't exercise all failure modes.
- Memory-specific defects: Stuck-at cell, transition fault, coupling fault, address decoder fault.
- A single SoC may contain 1,000+ SRAM instances — each needs testing.
- External ATE testing of all memories would require hours — MBIST completes in milliseconds.
**March Algorithm Patterns**
| Algorithm | Complexity | Faults Detected |
|-----------|-----------|----------------|
| March C- | 10N | Stuck-at, transition, coupling |
| March B | 17N | +Address decoder faults |
| March SS | 22N | +Static coupling faults |
| Checkerboard | 4N | Data pattern sensitivity |
| Walking 1/0 | N² | All coupling — very slow |
- **N** = number of memory words. March C- on 256KB SRAM (64K words): 640K operations — milliseconds at GHz clock.
**March C- Algorithm** (most popular):
- ⇑(w0) — Write 0 to all addresses ascending.
- ⇑(r0, w1) — Read 0, write 1, ascending.
- ⇑(r1, w0) — Read 1, write 0, ascending.
- ⇓(r0, w1) — Read 0, write 1, descending.
- ⇓(r1, w0) — Read 1, write 0, descending.
- ⇓(r0) — Read 0, descending.
**MBIST Architecture**
- **BIST Controller**: FSM that sequences the march algorithm.
- **Address Generator**: Generates address patterns (ascending, descending, Gray code).
- **Data Generator**: Generates data patterns (all-0, all-1, checkerboard, data background).
- **Comparator**: Compares read data against expected — flags failures.
- **Diagnostic Register**: Stores failing address and data for repair analysis.
**Memory Repair with MBIST**
- MBIST identifies failing rows/columns → recorded in repair register.
- **Redundancy repair**: Activate spare rows/columns to replace failing ones.
- Repair information stored in eFuse or anti-fuse — programmed once after test.
- Typical: 2-4 redundant rows + 1-2 redundant columns per SRAM instance.
Memory BIST is **indispensable for modern SoC manufacturing** — with memories dominating die area, MBIST provides fast, comprehensive test and repair capability that directly determines chip yield and the economics of high-volume production.