low power design technique

**Low-Power Design Techniques** are the **hierarchy of circuit and architectural strategies that reduce dynamic power (switching activity × capacitance × V² × frequency) and static power (leakage current × supply voltage) in digital chips — critical because power consumption determines battery life in mobile devices, thermal design in data centers, and energy cost as the dominant operational expense for large-scale computing infrastructure**. **Power Components** - **Dynamic Power**: P_dyn = α × C_load × V_DD² × f_clk. Proportional to switching activity (α), load capacitance, voltage squared, and frequency. Dominates in active operation. - **Short-Circuit Power**: Momentary current through both PMOS and NMOS during signal transitions. Typically 5-10% of dynamic power. - **Leakage Power**: P_leak = I_leak × V_DD. Subthreshold leakage and gate tunneling current flow continuously, even when idle. At advanced nodes (5nm, 3nm), leakage can exceed 30-50% of total chip power. **Dynamic Power Reduction** - **Clock Gating**: Disabling the clock to inactive registers eliminates their switching power. The most effective single technique — typically reduces clock tree power by 40-60%. Synthesis tools insert clock gating cells (ICG) automatically when they detect enable conditions. Fine-grained clock gating: per-register group. Coarse-grained: per-functional-unit. - **Operand Isolation**: Gate the inputs to idle arithmetic units, preventing unnecessary value changes from propagating through the datapath. Complements clock gating by reducing combinational switching. - **Bus Encoding**: Gray code or one-hot encoding on high-activity buses reduces switching activity. Memory address buses benefit from Gray coding because sequential addresses differ in only one bit. **Voltage and Frequency Scaling** - **Multi-Voltage Design**: Different blocks operate at different voltages. Performance-critical blocks (CPU core) at high voltage; low-speed peripherals at low voltage. Requires level shifters at domain crossings. - **DVFS (Dynamic Voltage-Frequency Scaling)**: Software adjusts voltage and frequency based on workload demand. Reducing voltage by 20% reduces dynamic power by 36% (V² relationship). Governed by P-states in ACPI. - **Adaptive Voltage Scaling (AVS)**: Closed-loop system with on-die performance monitors that adjusts supply voltage to the minimum needed for the current operating frequency, compensating for process variation. Saves 10-20% power versus fixed worst-case voltage. **Leakage Reduction** - **Power Gating**: Physically disconnects the supply from inactive blocks using header (PMOS) or footer (NMOS) sleep transistors. Reduces leakage to near zero. Requires retention flip-flops for state preservation and a wake-up sequence (10-100 us) to restore power. - **Multi-Threshold Voltage (Multi-Vt)**: Use high-Vt cells on non-critical paths (lower leakage) and low-Vt cells only on timing-critical paths (faster but leakier). Synthesis optimizes the Vt mix to meet timing with minimum leakage. - **Body Biasing**: Applying a reverse body bias (RBB) increases effective threshold voltage, reducing leakage during standby. Forward body bias (FBB) decreases Vt for performance boost during active operation. **Low-Power Design is the engineering response to the fundamental physics of CMOS scaling** — the discipline that ensures each new process generation's increased transistor density translates into more useful computation per watt rather than simply more heat.