low power design upf ieee 1801

**Low-Power Design with UPF (IEEE 1801)** is **the standardized methodology for specifying power intent — including voltage domains, power states, isolation strategies, retention policies, and level-shifting requirements — separately from the RTL functional description, enabling EDA tools to automatically implement, verify, and optimize power management structures across the entire design flow** — from RTL simulation through synthesis, place-and-route, and signoff. **UPF Power Intent Specification:** - **Power Domains**: logical groupings of design elements that share a common power supply and can be independently controlled (powered on, powered off, or voltage-scaled); each domain is defined with its primary supply and optional backup supply for retention - **Power States**: enumeration of all valid supply voltage combinations across the chip; a power state table (PST) defines which domains are on, off, or at reduced voltage in each operating mode, ensuring that all transitions between states are explicitly defined - **Supply Networks**: UPF models power rails as supply nets with voltage values; supply sets associate a power/ground pair with each domain; multiple supply sets enable multi-voltage operation where different domains run at different VDD levels - **Isolation Strategy**: when a powered-off domain drives signals into an active domain, isolation cells clamp the crossing signals to known values (logic 0, logic 1, or latched value); UPF specifies isolation cell type, placement, and enable signal for every crossing **Implementation Elements:** - **Isolation Cells**: combinational gates inserted at power domain boundaries that force outputs to a safe value when the source domain is powered down; AND-type clamps to 0, OR-type clamps to 1, latch-type holds the last active value - **Level Shifters**: voltage translation cells inserted when signals cross between domains operating at different VDD levels; required for both up-shifting (low-to-high voltage) and down-shifting (high-to-low voltage) crossings - **Retention Registers**: special flip-flops with a shadow latch powered by an always-on supply that preserves state during power-down; UPF specifies which registers require retention using set_retention commands and defines save/restore control signals - **Power Switches**: header (PMOS) or footer (NMOS) transistors that connect or disconnect a domain's virtual VDD/VSS from the global supply; UPF defines switch cell type, control signals, and the daisy-chain enable sequence for rush current management **Verification Flow:** - **UPF-Aware Simulation**: simulators model power state transitions, checking that isolation cells activate before power-down and that retention save/restore sequences execute correctly; signals from powered-off domains propagate as X (unknown) to expose missing isolation - **Formal Verification**: formal tools exhaustively verify that no signal path exists from a powered-off domain to active logic without proper isolation; level shifter completeness is checked for all voltage-crossing paths - **Power-Aware Synthesis**: synthesis tools read UPF alongside RTL to automatically insert isolation cells, level shifters, and retention flops; the synthesized netlist includes all power management cells with correct connectivity - **Signoff Checks**: static verification confirms that all UPF intent is correctly implemented in the final layout; power domain supply connections, isolation enable timing, and retention control sequences are validated against the UPF specification Low-power design with UPF is **the industry-standard framework that separates power management intent from functional design, enabling systematic implementation and verification of complex multi-domain power architectures — essential for mobile, IoT, and data center chips where power efficiency determines product competitiveness and battery life**.