low power simulation
**Power-Aware Simulation and UPF Verification** is the **specialized verification methodology that simulates the behavior of a chip design with its power management architecture (power gating, voltage scaling, retention) actively modeled** — verifying that isolation cells correctly clamp outputs when a domain is powered off, retention registers properly save and restore state across power cycles, and level shifters correctly translate signals between voltage domains, catching power-related bugs that standard functional simulation completely misses.
**Why Power-Aware Simulation**
- Standard simulation: All signals are either 0 or 1 → power domains always assumed ON.
- Reality: Blocks power-gate (shut off) → outputs become undefined (X) → must be isolated.
- Without power simulation: Cannot verify isolation cells, retention, power sequencing.
- Power bugs: #1 cause of silicon failure in SoC designs with complex power management.
**UPF (Unified Power Format)**
```tcl
# Define power domains
create_power_domain PD_CORE -elements {u_cpu_core}
create_power_domain PD_GPU -elements {u_gpu} -shutoff_condition {!gpu_pwr_en}
create_power_domain PD_ALWAYS_ON -elements {u_pmu u_wakeup}
# Define power states
add_power_state PD_GPU -state ON {-supply_expr {power == FULL_ON}}
add_power_state PD_GPU -state OFF {-supply_expr {power == OFF}}
# Isolation
set_isolation iso_gpu -domain PD_GPU \
-isolation_power_net VDD_AON \
-clamp_value 0 \
-applies_to outputs
# Retention
set_retention ret_gpu -domain PD_GPU \
-save_signal {gpu_save posedge} \
-restore_signal {gpu_restore posedge}
```
**What Power-Aware Simulation Checks**
| Check | What | Consequence If Missed |
|-------|------|----------------------|
| Isolation clamping | Outputs from OFF domain clamped to 0/1 | Floating signals → random behavior |
| Retention save/restore | State saved before OFF, restored after ON | Data loss across power cycle |
| Level shifter function | Signal correctly translated between voltages | Logic errors at domain boundaries |
| Power sequencing | Domains powered on/off in correct order | Short circuits, latch-up |
| Supply corruption | Signals driven by OFF supply become X | Corruption propagation |
**X-Propagation in Power Simulation**
```svg
```
- Without isolation: A receives X from B → X propagates through A → false failures OR masked real bugs.
- Correct isolation: A receives clamped value (0 or 1) → design functions correctly.
**Power-Aware Simulation Flow**
1. Read RTL + UPF (power intent).
2. Simulator creates supply network model (power switches, isolation cells, retention cells).
3. Run testbench with power state transitions:
- Power on GPU → run workload → save state → power off GPU → verify isolation.
- Power on GPU → restore state → verify data integrity.
4. Check for:
- No X propagation to active domains.
- Correct isolation values.
- State retention across power cycles.
- Correct power-on reset behavior.
**Common Power Bugs Found**
| Bug | Symptom | Root Cause |
|-----|---------|------------|
| Missing isolation cell | X propagation on output | UPF incomplete |
| Wrong clamp value | Downstream logic gets wrong value | Clamp should be 1 not 0 |
| Missing retention | State lost after power cycle | Register not flagged for retention |
| Incorrect sequence | Short circuit during transition | Power-on before isolation enabled |
| Level shifter missing | Signal at wrong voltage level | Cross-domain signal not identified |
**Verification Completeness**
- Formal UPF verification: Statically checks all domain crossings have isolation/level shifters.
- Simulation: Dynamically verifies behavior during power transitions.
- Both needed: Formal catches structural issues, simulation catches sequencing bugs.
Power-aware simulation is **the verification methodology that prevents the most expensive class of silicon bugs in modern SoCs** — with power management involving dozens of power domains, hundreds of isolation cells, and complex power sequencing protocols, the failure to properly verify power intent through UPF-driven simulation is the leading cause of first-silicon failures in complex SoC designs, making power-aware verification a non-negotiable requirement for tapeout signoff.