Scope This Series to Addressing and Applications Not the Fabricationfixed Bit Again
# Scope This Series to Addressing and Applications, Not the Fabrication-Fixed Bit Again
## 1. Draw the Boundary Before Writing a Single Mask-ROM Sentence
This series covers how a mask-programmed read-only memory chip selects a row of fixed bits, and what that fixed bit pattern was actually used for beyond storing a microprocessor's user program — not, again, the fact that a mask ROM bit is fixed at fabrication. That specific mechanism, the presence or absence of a fabricated connection determining a stored bit, is already told in full in `microprocessor_1971_step06`, which also carries its own dedicated DRAM-versus-mask-ROM comparison table and a diagram of one 4004 CPU paired with three differently masked 4001 ROMs for three different products. Nothing in this series retells that mechanism or that comparison.
The commercial-niche and packaging-cost side of the story is likewise already told: `eprom_eeprom_history_step08` and `step10` cover, in concrete detail, why mask ROM's plain plastic package and absence of program/erase circuitry made it the cheaper choice once a product's firmware was finalized for high-volume shipment, against EPROM's windowed ceramic package and development-time erasability. This series does not re-derive that cost comparison either.
What is genuinely untold on this site, and what this series exists to tell, is the internal addressing architecture a mask ROM actually used to turn an address into a row of bits — the diode-matrix and transistor-matrix schemes, told at the architectural level and contrasted against DRAM's own RAS/CAS addressing and SRAM's own word-line/bit-line addressing without retelling either of those series' own cell-level mechanisms — plus the real photomask design and mask-set economics (lead time, tape-out commitment, respin cost), and three named applications that have nothing to do with the 4001's user-facing program storage: character-generator ROMs, game-cartridge ROMs, and microcode ROM.
## 2. Preview the Fourteen-Step Arc
Steps 2–4 cover the addressing architecture itself: the diode-matrix row-select scheme, the transistor-matrix refinement that displaced it, and an architectural-level contrast against DRAM and SRAM addressing. Steps 5–7 cover the photomask economics: design and fabrication lead time, the cost of a respin when even one bit is wrong after tape-out, and exactly what a later metal-only mask layer can and cannot still fix. Steps 8–9 cover character-generator ROMs as a named glyph-lookup application. Steps 10–11 cover game-cartridge ROMs as a named commercial product category. Steps 12–13 cover microcode ROM as a CPU's own internal control-sequence store, genuinely distinct from the 4001's user program. Step 14 closes by naming, not retelling, how this series completes the mask-ROM picture alongside `microprocessor_1971` and `eprom_eeprom_history`.
This series assumes the reader already knows what a mask-programmed bit is; it spends its budget entirely on how that bit gets selected and what it was actually used to store.