Replace the Diode with a Transistor and Displace the Diode Matrix Commercially
# Replace the Diode With a Transistor and Displace the Diode Matrix Commercially
## 1. Put a Transistor at Each Crossing Instead of a Diode
The transistor-matrix mask ROM kept the same row-decode, column-sense addressing shape as the diode matrix, but replaced the passive diode at each crossing with a transistor whose gate connection (present or absent, exactly as the mask defined it) controlled whether that crossing conducted when its row was activated. The bit is still fixed by what the mask fabricated at that crossing — a present gate connection reads as one bit value, an absent one reads as the other — so this is a genuinely different implementation choice within "mask ROM," not a renaming of the diode scheme.
The row-select and column-sense addressing logic around the array barely changed; what changed was the device sitting at each bit position.
## 2. Understand Why the Transistor Won
A diode conducts whenever its row is driven, with a voltage drop that depends on the diode's own characteristics and that degrades as more diodes on a row try to conduct at once — a real loading problem as array size grew. A transistor at each crossing, driven by the same row-select line into its gate (when present) or isolated from it (when absent), gave each column a cleaner, more uniform switching threshold and a smaller cell footprint as fabrication geometries shrank, because a MOS transistor's own gate-oxide process was already the array's dominant fabrication step for other reasons. The diode matrix did not fail outright; it was simply outcompeted on density and signal quality as transistor-based array fabrication matured, in the same general direction that pushed DRAM toward its own transistor-based cell and SRAM toward its own transistor pair — a parallel industry trend, not a shared mechanism, since each memory type's transistor plays a structurally different role in its own cell.
Step 4 contrasts this row-select-and-sense addressing shape, used by both the diode and transistor matrix, against DRAM's RAS/CAS scheme and SRAM's word-line/bit-line scheme, architecturally.