Deep Submicron CMOS Scaling 1990s Replace Locos with Shallow Trench Isolation
# Deep Submicron CMOS Scaling (1990s): Step 13 — Replace LOCOS With Shallow Trench Isolation
## 1. Why LOCOS Ran Out of Room
The `mosfet_scaling_1970s` series' step 7 established LOCOS (local oxidation of silicon) as the standard field-isolation technique separating neighboring transistors, growing a thick field oxide through a nitride mask to block unwanted channel formation between devices. LOCOS's oxidation is inherently lateral as well as vertical — oxidant diffuses sideways under the edge of the nitride mask during the thermal growth, producing a tapered oxide encroachment known as the "bird's beak" that consumes active-area silicon beyond the nominally masked boundary. At 1980s geometries, the bird's beak's lateral extent was a tolerable area tax; at deep submicron 1990s geometries, where devices and their required isolation spacing were both shrinking toward LOCOS's fixed-ish bird's-beak dimension, the encroachment started consuming an unacceptably large fraction of the shrinking cell area, and the active-area edge rounding it produced also complicated controlling channel width precisely at these dimensions.
## 2. The Shallow Trench Isolation Alternative
Shallow trench isolation (STI) replaces thermal field-oxide growth with a purely geometric approach: etch a trench of the desired isolation width directly into the silicon between active areas, deposit a dielectric (commonly CVD oxide) to fill the trench, and planarize the surface back to flat — the chemical-mechanical polishing capability from Step 12 doing exactly that planarization job here as well. Because the trench's width and depth are set by lithography and etch, not by a lateral thermal diffusion process, STI has essentially no bird's-beak-equivalent encroachment: the isolation boundary is where the trench was etched, full stop, which lets isolation width shrink in step with everything else at a given node rather than being bottlenecked by a geometry LOCOS could not shrink as fast.
## 3. What STI Trades Away
STI's vertical sidewalls, unlike LOCOS's gradually tapered field-oxide edge, create sharper corners at the top of the active-area/trench boundary, which can locally concentrate electric field at the gate edge directly above that corner and create a parasitic leakage or threshold-shift effect at the very edge of the transistor if the corner is left too sharp. 1990s STI process development spent considerable effort on corner rounding techniques — controlled etch profiles and oxidation steps specifically aimed at softening this corner — to recover the clean isolation edge behavior LOCOS's gradual taper gave for free, in exchange for the area efficiency STI's lack of a bird's beak provided.
## 4. Why STI Became the Standard Despite the New Corner Problem
The area savings STI offered at deep submicron pitches were large enough, and the corner-rounding fix tractable enough with sufficient process development, that STI displaced LOCOS as the mainstream isolation technique across 1990s deep submicron logic processes, even though LOCOS's simpler, purely-thermal process had no equivalent corner-engineering burden. This is a recurring pattern in this series: nearly every deep submicron fix (LDD grading, salicide, STI) trades a new, manageable second-order problem for the removal of a first-order area or reliability constraint that scaling had turned from tolerable into limiting.