memory coalescing

Memory coalescing is a critical GPU optimization where adjacent threads access adjacent memory locations, enabling the hardware to combine multiple memory requests into single, efficient transactions. Modern GPUs execute threads in groups (warps of 32 threads on NVIDIA, wavefronts of 64 on AMD), and the memory controller can coalesce individual thread requests into 128-byte cache line accesses. Coalesced access achieves near-peak memory bandwidth, while scattered access patterns trigger separate transactions per thread, reducing effective bandwidth by 10-32x. Programming for coalescing requires data layout awareness: array-of-structures (AoS) patterns typically scatter access, while structure-of-arrays (SoA) enables coalescing. Thread indexing must align with data organization: thread N should access element N. Strided access patterns (threads accessing every Nth element) defeat coalescing and should be avoided or solved through shared memory staging. The hardware automatically detects coalescing opportunities within warps. Performance profiling tools report coalescing efficiency metrics, guiding optimization. Achieving high memory coalescing often determines whether GPU code achieves 10% or 90% of theoretical memory throughput.