memory compiler design
**Memory Compiler Design** is the **creation of parameterized generators that automatically produce custom SRAM, register file, ROM, and other memory instances with user-specified configurations** — generating complete layouts, timing models, and verification collateral that are foundry-DRC/LVS clean.
Memory compilers are essential: embedded memories occupy 30-70% of modern SoC die area, each design requires hundreds of unique instances, and manual design of each is infeasible.
**Generated Memory Architecture**:
| Component | Function | Key Choices |
|-----------|----------|-------------------|
| **Bitcell array** | Storage | 6T/8T SRAM, HD vs HP |
| **Row decoder** | Wordline selection | Pre-decoder + final stage |
| **Column mux** | Bit selection | 4:1, 8:1, 16:1 |
| **Sense amplifier** | Read sensing | Voltage or current mode |
| **Write driver** | Write data | Write-assist techniques |
| **Control logic** | Timing | Self-timed or clock-based |
| **Redundancy** | Yield repair | Spare rows/columns + fuse |
**Compiler Structure**: **Bitcell library** (foundry-qualified layouts), **peripheral templates** (parameterized leaf cells for decoders, muxes, sense amps), **assembly engine** (algorithmic floorplanning/routing based on parameters), **characterization engine** (SPICE across PVT corners for timing/power models), and **verification engine** (DRC/LVS on generated instances).
**Key Parameters and Impact**: **Words x Bits** (array aspect ratio, decoder complexity), **column mux ratio** (higher CM = smaller area but slower), **number of ports** (more ports increase bitcell size to 8T-10T), **banking** (reduces loading, enables partial activation), **write assist** (negative bitline, wordline underdrive for reliable write at low VDD), **read assist** (wordline pulsing, replica bitline timing).
**Advanced Node Challenges**: **Bitcell scaling stalls** (6T SRAM area scaling slows), **read/write margins** degrade with variability (sigma-based Vmin analysis on millions of bitcells), **FinFET/GAA quantization** limits optimization, and **EUV variability** affects matching. These drive innovations: buried power rail SRAM, backside contacts, and hybrid SRAM/eDRAM architectures.
**Memory compiler technology is the invisible productivity multiplier in SoC design — generating hundreds of silicon-proven memory instances in hours rather than months.**