memory compiler sram

**Memory Compiler and SRAM Design** is the **EDA tool and custom circuit design discipline that generates optimized, foundry-qualified memory macros (SRAM, register files, ROM, CAM) for any specified configuration (word depth, bit width, number of ports) — where SRAM typically consumes 30-60% of a modern SoC's die area, and the bitcell design and sense amplifier performance directly determine the minimum operating voltage (Vmin), access time, and overall chip yield**. **The 6T SRAM Bitcell** The standard SRAM cell uses 6 transistors: two cross-coupled inverters (4T) forming a bistable latch that stores one bit, plus two access transistors (2T) controlled by the wordline that connect the latch to the bitlines for read/write. **Design Constraints (The SRAM Stability Triangle)** - **Read Stability (SNM)**: During read, the access transistors create a voltage divider with the latch transistors, disturbing the stored value. If the read disturbance exceeds the Static Noise Margin (SNM), the cell flips — a destructive read. Read stability requires the pull-down NMOS to be stronger than the access transistor (cell ratio, typically >1.4). - **Write Ability (WM)**: During write, the bitline must overpower the storing inverter to flip the cell. Write margin requires the access transistor to be stronger than the pull-up PMOS (pull-up ratio, typically <1.8). - **Hold Stability**: With wordline off, the cross-coupled inverters must hold state against noise and leakage. Determined by the latch SNM. - **The Conflict**: Read stability wants weak access transistors; write ability wants strong access transistors. This fundamental tension drives bitcell sizing, variant selection (6T, 8T, 10T), and assist circuit design. **Memory Compiler Function** Given user inputs (depth, width, mux ratio, number of ports, operating corners), the memory compiler: 1. Tiles the bitcell array (custom-designed, foundry-qualified bitcells at minimum area). 2. Places row decoders, column mux, sense amplifiers, write drivers, and control logic. 3. Generates the physical layout (GDS), timing model (.lib), behavioral model (Verilog), and abstract (LEF) for the specified configuration. 4. Characterizes timing (setup, hold, clock-to-Q, access time) and power at all specified PVT corners. **Assist Circuits for Low-Vmin** - **Wordline Underdrive**: Reduce wordline voltage during read to weaken access transistors, improving read SNM. - **Negative Bitline Write Assist**: Drive the bitline below VSS during write, strengthening the write path. - **Supply Boosting**: Temporarily raise SRAM array VDD during access for improved margins. - **Bitcell Variants**: 8T (separate read port eliminates read disturb) and 10T (fully differential separate read) cells trade area for stability. Memory Compiler and SRAM Design is **the custom silicon engineering that fills most of the chip** — designing the densest, most electrically-constrained structures on the die and generating thousands of unique macro configurations to support the diverse memory needs of modern SoCs.