Microprocessor 1971 Choose 4 Bit Word Pin Transistor Budget

# Choose a 4-Bit Word to Fit the Pin and Transistor Budget

## 1. Make the Native Word Match the Calculator's Decimal Digit

The Intel 4004 chose a four-bit processing word because four binary bits can encode the ten values of one decimal digit while keeping every repeated datapath structure narrow enough for an approximately 2,300-transistor processor. Busicom's calculator workload was organized around decimal digits, so a four-bit register or arithmetic slice could hold one binary-coded-decimal digit directly: codes $0000_2$ through $1001_2$ represent decimal 0 through 9, while the remaining six combinations are available to the architecture rather than requiring a wider native arithmetic path.

$$2^4=16\geq10, \qquad 2^3=8<10$$

Four bits are therefore the minimum binary width capable of representing an entire decimal digit. The choice does not mean the processor can address only sixteen locations or execute only sixteen instructions. It means the accumulator, arithmetic path, and basic data units operate four bits at a time; wider addresses and instruction encodings are assembled or transferred across multiple groups.

Four Bits Are the Narrowest Complete Decimal-Digit Word calculator workload fit on the left; repeated processor hardware on the right DECIMAL DIGIT REQUIREMENT 0000 0001 0010 ··· 1001 012…9 3 bits: 8 states · insufficient 4 bits: 16 states · one full decimal digit minimum complete BCD-oriented word FOUR-BIT PROCESSOR SLICE bit 0bit 1bit 2bit 3 ALU + ACCUMULATOR + REGISTERS four parallel bit positions every extra native bit repeats logic and routing within a finite transistor and die-area budget workload fit and implementation economy point to the same four-bit native word

## 2. Keep the Package at Sixteen Pins by Reusing Four Signal Lines Across Time

The processor was packaged with sixteen pins, far fewer than would be needed to expose separate parallel connections for a wider address, a full instruction, and data simultaneously. The MCS-4 architecture instead reused a four-line bus across successive time slots. Those same physical conductors could carry groups belonging to a wider address, instruction transfer, or data exchange at different moments in the machine cycle.

If a quantity of width $W$ is transferred over a bus of width $B$, the minimum number of groups is

$$N_{groups}=\left\lceil\frac{W}{B}\right\rceil$$

so a twelve-bit address requires three four-bit groups and an eight-bit instruction byte requires two. Serialization costs cycles and control, but avoids dedicating twelve address pins plus separate data and instruction pins. The four-bit choice therefore shapes both the internal datapath and the external system interface without confusing the two.

A Four-Line Bus Carries Wider Quantities in Successive Groups pin economy is achieved by multiplexing function across time 4004 CPU 16-PIN PACKAGE four multiplexed lines SAME FOUR WIRES · DIFFERENT TIME SLOTS ADDRESSbits 0–3 ADDRESSbits 4–7 ADDRESSbits 8–11 NEXT4-bit group time advances → physical bus width stays four narrow pins do not limit the address to four bits; they serialize wider information the cost is additional time slots and control instead of additional package connections

## 3. Four Bits Are an Architectural Compromise, Not a Claim About Universal Computing Width

An eight-bit or wider native datapath can process larger binary quantities with fewer passes, but it also repeats more arithmetic circuitry, storage, control fan-out, and internal wiring. In the 4004's 10-micrometer PMOS technology and roughly 2,300-transistor implementation, widening every native data structure would have competed directly with the control, instruction sequencing, registers, and interfaces required to put a complete programmable processor on one die.

The four-bit decision succeeds because the original calculator workload supplies a natural unit—one decimal digit—while time multiplexing lets a narrow physical interface carry wider architectural information. The design spends time to save transistors, die area, and package pins. That is the first explicit systems trade in this series: general programmability is preserved, but peak work per cycle is bounded to make the entire processor manufacturable as one chip.

Step 2 fixes the processor's native data width and its external transfer granularity. The next step can now build the arithmetic core around that decision: a four-bit accumulator and arithmetic-logic path capable of executing the operations encoded by the stored program.

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