Microprocessor 1971 Multiplex Address and Data Same Pins

# Multiplex Address and Data Onto the Same Pins: Time-Share One Physical Path Instead of Dedicating Separate Ones

## 1. Give the Four Bus Lines a Different Meaning in Each Clock Phase

The Intel 4004 did not dedicate one set of package pins to addresses and another to instructions and data. It reused the same four lines, D0–D3, in an ordered sequence of time slots. During the address portion of a machine cycle, the processor presents a twelve-bit address as three successive four-bit groups. During later portions, the same conductors carry instruction or data groups. The pins remain four bits wide; their meaning changes with the phase.

The interface is therefore defined by both voltage and time:

$$\operatorname{role}(D_{3:0},t)= \begin{cases} \text{address group}, & t\in\{A1,A2,A3\}\\ \text{instruction group}, & t\in\{M1,M2\}\\ \text{execution or data transfer}, & t\in\{X1,X2,X3\} \end{cases}$$

The eight phases—A1, A2, A3, M1, M2, X1, X2, and X3—form one 4004 instruction cycle. This is not merely a narrow bus sending a long number slowly. It is a shared path whose semantic role is scheduled: the system knows whether a four-bit pattern is an address, an instruction fragment, or a data transfer because it knows when that pattern appears.

One Four-Bit Path Performs Three Jobs Across Time the phase identifies what D3–D0 mean at each instant MACHINE CYCLE time A1addressnibble 1CPU → bus A2addressnibble 2CPU → bus A3addressnibble 3CPU → bus M1instructionfirst groupmemory → bus M2instructionsecond groupmemory → bus X1executeor transferrole by instruction X2executeor transferrole by instruction X3executeor transferrole by instruction 12-BIT ADDRESS8-BIT INSTRUCTIONEXECUTION WINDOW D3–D0 never become wider; the schedule changes their meaning three address groups + two instruction groups + three execution phases

## 2. Latch Each Group, Then Transfer Ownership Before the Bus Changes Direction

Time-sharing works only if information survives after its time slot ends. The receiving ROM or RAM circuitry captures the address groups in latches during A1–A3. Once captured, that address remains available internally even while D0–D3 are reassigned to the instruction transfer. The bus carries the next role; the latch preserves the previous role's result.

The interface also needs an ownership rule. During an address phase, the processor enables its output drivers and the memory devices receive. When the selected memory returns an instruction group, the processor stops driving and becomes the receiver. A phase decoder and chip-selection logic coordinate that handoff so two sources do not impose different voltages on the same conductor.

$$N_{\mathrm{enabled\ drivers}}(t)\leq 1$$

That inequality is the electrical condition behind the architectural abstraction. If two active drivers disagree, current flows between them and the bus value is no longer trustworthy. Multiplexing therefore replaces dedicated pins with latches, output-enable control, and a timing contract—not with ambiguity.

Latches Preserve Meaning While Bus Ownership Changes the phase schedule coordinates capture, release, and return 4004 PROCESSOR OUTPUT DRIVERSenabled during address INPUT REGISTERcaptures returned group SHARED D3–D0 BUS one physical path · one active source MCS-4 MEMORY ADDRESS LATCHESretain A1–A3 groups RETURN DRIVERSenabled in assigned phase A1–A3: CPU DRIVES · MEMORY CAPTURES M1–M2: MEMORY DRIVES · CPU CAPTURES PHASE DECODER + CHIP SELECT enable one source · place every other source in receive/released state captured state remains valid after the shared wires move to their next role

## 3. Spend Timing and Control to Save Package Connections

A non-multiplexed interface is conceptually simpler: address wires remain address wires, data wires remain data wires, and both may exist concurrently. The 4004's interface instead makes communication sequential. A memory component cannot interpret D3–D0 from voltage alone; it must follow the common cycle, capture the right group at the right phase, and release or drive the bus at the specified handoff.

That added protocol is the price of fitting a programmable processor system around a sixteen-pin CPU package. The design saves physical connections and routing by spending time, latches, and coordinated control. More importantly, it establishes a general systems idea: a physical resource need not have one permanently assigned meaning when a reliable schedule can separate its uses.

Step 3 has now delivered the fetched instruction to an input register as two timed four-bit groups. Step 4 can use the silicon-gate logic already established in 1967 to decode those captured bits into the internal control signals that select registers, arithmetic operations, and data movement.

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