Microprocessor 1971 Clock Multiplexing Multi Phase Timing

# Confront the Clock: Why Multiplexing Forces a Multi-Phase Timing Scheme

## 1. Distinguish the Two Electrical Clock Phases From the Eight Bus Periods

The MCS-4 timing system has two different layers that must not be confused. Two externally supplied, non-overlapping clock phases—$\phi_1$ and $\phi_2$—operate the dynamic PMOS circuitry. Above them, the 4004 counts eight clock periods to create the named machine-cycle states A1, A2, A3, M1, M2, X1, X2, and X3. Each named state contains an ordered $\phi_1$/$\phi_2$ sequence.

$$T_{instruction}=8T_{clock}=8(1.35\ \mu\mathrm{s})=10.8\ \mu\mathrm{s}$$

The Intel MCS-4 manual specifies a 10.8-microsecond basic instruction cycle at a 750-kilohertz nominal clock description. One-word instructions occupy the eight periods; the five double-length instruction forms occupy two complete machine cycles. The processor also emits SYNC once every eight periods so every 4001 ROM and 4002 RAM can align its own internal state counter with the CPU.

Two Clock Phases Advance Eight Named Machine States electrical phasing below · bus meaning above · SYNC aligns every MCS-4 chip ONE 10.8 µs INSTRUCTION CYCLE A1 A2 A3 M1 M2 X1 X2 X3 φ1 φ2 the gap between φ1 and φ2 is deliberate: the phases do not overlap SYNC boundary two non-overlapping electrical phases are repeated inside every named bus period

## 2. Use Time Windows to Prevent One Shared Bus From Having Two Meanings at Once

Multiplexing makes timing part of the interface definition. During A1–A3, the CPU owns D3–D0 and the memories capture address groups. During M1–M2, the selected ROM owns those same conductors and the CPU captures OPR and OPA. During X1–X3, ownership and meaning depend on the decoded instruction. A value without its phase label is incomplete information.

Every transfer needs three ordered intervals:

1. The previous driver releases the bus.
2. The selected source establishes a new four-bit value.
3. The receiving latch captures that value only after it has settled.

Non-overlapping clock phases create separation between dynamic-node operations, while the eight-state sequence provides the larger communication schedule. The bus output buffers add a third, floating state so inactive chips neither assert a zero nor a one. Intel's manual states the governing rule directly in electrical terms: only one output buffer may drive a data line at a time, although multiple input buffers may observe it.

$$\sum_j E_j(t)\leq1$$

where $E_j=1$ means device $j$ has enabled its output driver. The clock and phase decoder enforce that invariant across the whole chip set.

A Safe Handoff Separates Release, Drive, and Capture the shared bus changes owner without allowing conflicting output drivers time 1 · RELEASEold source disables outputbus enters floating intervalNO RETAINED OWNERSHIP 2 · DRIVE + SETTLEnew source enables outputfour lines reach valid levelsONE ACTIVE DRIVER 3 · CAPTUREreceiver samples stable valuelatch preserves the groupSTATE MAY NOW CHANGE PHASE = MEANING + OWNER + CAPTURE PERMISSION the clock makes a narrow physical path behave like several logically distinct channels

## 3. Accept Timing Overhead as the Cost of a Coordinated Chip Set

A dedicated wide interface could expose an address and an instruction simultaneously, reducing the need for serialization. The MCS-4 instead spends five of its eight basic periods distributing the address and fetching the instruction before the X periods complete execution or external transfer. That schedule is not idle overhead: it is the mechanism that lets a 16-pin CPU coordinate separate ROM and RAM devices through four shared data lines.

The two-phase clock also supports the dynamic storage and logic used inside the early PMOS chips. Charge-based internal nodes must be preconditioned and evaluated in an ordered way; overlapping clock phases could connect paths that were meant to be isolated. Thus the clock scheme serves both the external multiplexed protocol and the internal dynamic implementation.

Step 7 establishes a deterministic instruction rhythm: SYNC, three address periods, two instruction periods, and three execution periods. Step 8 can now measure the resulting 10.8-microsecond instruction cycle against a discrete-logic implementation using the project's 1960 cost-per-function framework, without pretending that clock frequency alone captures the system advantage.

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