Microprocessor 1971 Measure Instruction Cycle Discrete Logic

# Measure the Instruction Cycle Against a Discrete-Logic Equivalent: Count System Cost, Not Clock Speed Alone

## 1. Measure What the 4004 Actually Completes in 10.8 Microseconds

At the documented MCS-4 timing, a basic one-word instruction occupies eight clock periods of approximately 1.35 microseconds each, producing a 10.8-microsecond instruction cycle. Five double-length instruction forms require two machine cycles, or 21.6 microseconds, because their second program byte must be fetched in the following cycle.

This rate is not the same as 92,600 complete calculator operations per second. A decimal addition routine must fetch operands, add corresponding digits, apply decimal adjustment, store results, advance addresses, and repeat across all digit positions. Conversely, one machine cycle accomplishes more than a single transistor switch: it addresses program memory, fetches and decodes an instruction, and performs the selected state transition across a coordinated chip set.

## 2. Define the Discrete Equivalent Before Claiming a Speed Comparison

A discrete-logic “equivalent” is not one uniquely defined machine. It might be a purpose-built calculator datapath optimized for one operation, or it might reproduce the 4004's program counter, register file, instruction decoder, branching, arithmetic, memory control, and I/O behavior from many separate logic packages. Those targets answer different questions.

A fixed-function network can eliminate instruction fetch and decode, so its chosen arithmetic path may produce one result with less sequencing. But it is not functionally equivalent to a programmable processor. A true functional comparison must reproduce the stored-program behaviors: changeable instruction order, conditional control flow, subroutines, register selection, memory addressing, and multiple arithmetic and transfer operations.

For any implementation, application time should be measured as

where $N_i$ is the executed count of instruction or logic step $i$, and $T_i$ is its latency. Without a defined discrete circuit, logic family, clock, workload, and I/O boundary, a numerical “times faster” claim would be fabricated. The defensible 4004 result is its measured cycle; the defensible comparison is the change in how much system hardware must be assembled to obtain a given set of functions.

## 3. Apply the 1960 Cost-per-Function Test at the System Level

The project's 1960 series established that integration should be judged by cost per realized function, not merely by the purchase price of one component. For a processor system, the relevant cost includes device packages, board area, wiring, assembly, inspection, power distribution, and failures at inter-package connections:

The 4004 concentrates roughly 2,300 transistors and their internal connections in one CPU die. It still requires program memory and, where needed, data memory and I/O; “single-chip CPU” does not mean “complete product on one chip.” Yet replacing processor-scale board wiring with patterned on-die interconnect sharply changes the assembly problem. The same adder, registers, and control paths can realize many behaviors as the ROM instruction sequence changes, so their implementation cost is amortized across functions instead of duplicated as a dedicated path for each behavior.

The result is not that the 4004 must outrun every specialized discrete circuit. Its measurable basic cycle is 10.8 microseconds, and a hardwired path can avoid fetch overhead. The result is that a compact, manufacturable chip set can deliver a broad programmable function set with far fewer separately assembled logic boundaries. Step 9 will qualify that trade directly: flexibility and lower system cost per function against the raw speed available to fixed-purpose hardware.